Patents by Inventor Jagdish Narayan

Jagdish Narayan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030160246
    Abstract: An optoelectronic device such as an LED or laser which produces spontaneous emission by recombination of carriers (electrons and holes) trapped in Quantum Confinement Regions formed by transverse thickness variations in Quantum Well layers of group III nitrides.
    Type: Application
    Filed: July 26, 2002
    Publication date: August 28, 2003
    Inventors: Jagdish Narayan, Jinlin Ye, Schang-Jing Hon, Ken Fox, Jyh Chia Chen, Hong K. Choi, John C. C. Fan
  • Publication number: 20030160229
    Abstract: An optoelectronic device such as an LED or laser which produces spontaneous emission by recombination of carriers (electrons and holes) trapped in Quantum Confinement Regions formed by transverse thickness variations in Quantum Well layers of group III nitrides.
    Type: Application
    Filed: February 25, 2002
    Publication date: August 28, 2003
    Applicant: Kopin Corporation
    Inventors: Jagdish Narayan, Jinlin Ye, Schang-Jing Hon, Ken Fox, Jyh Chia Chen, Hong K. Choi, John C. C. Fan
  • Patent number: 6518077
    Abstract: An electronic device has an alloy layer containing magnesium oxide and at least one of zinc oxide and cadmium oxide and having a cubic structure on a substrate. The alloy layer may be directly on the substrate or, alternatively, one or more buffer layers may be between the alloy layer and the substrate. The alloy layer may be domain-matched epitaxially grown directly on the substrate, or may be lattice-matched epitaxially grown directly on the buffer layer. The cubic layer may also be used to form single and multiple quantum wells. Accordingly, electronic devices having wider bandgap, increased binding energy of excitons, and/or reduced density of growth and/or misfit dislocations in the active layers as compared with conventional III-nitride electronic devices may be provided.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: February 11, 2003
    Assignee: North Carolina State University
    Inventors: Jagdish Narayan, Ajay Kumar Sharma, John F. Muth
  • Publication number: 20030027293
    Abstract: The present invention describes a process for the isolation of polyhydroxybutyrate of the formula 1 1
    Type: Application
    Filed: March 28, 2001
    Publication date: February 6, 2003
    Applicant: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Manobjyoti Bordoloi, Bornali Borah, Purbali S. Thakur, Jagdish Narayan Nigam
  • Patent number: 6423983
    Abstract: An electronic device has an alloy layer containing magnesium oxide and at least one of zinc oxide and cadmium oxide and having a cubic structure on a substrate. The alloy layer may be directly on the substrate or, alternatively, one or more buffer layers may be between the alloy layer and the substrate. The alloy layer may be domain-matched epitaxially grown directly on the substrate, or may be lattice-matched epitaxially grown directly on the buffer layer. The cubic layer may also be used to form single and multiple quantum wells. Accordingly, electronic devices having wider bandgap, increased binding energy of excitons, and/or reduced density of growth and/or misfit dislocations in the active layers as compared with conventional III-nitride electronic devices may be provided.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: July 23, 2002
    Assignee: North Carolina State University
    Inventors: Jagdish Narayan, Ajay Kumar Sharma, John F. Muth
  • Publication number: 20020084466
    Abstract: An electronic device has an alloy layer containing magnesium oxide and at least one of zinc oxide and cadmium oxide and having a cubic structure on a substrate. The alloy layer may be directly on the substrate or, alternatively, one or more buffer layers may be between the alloy layer and the substrate. The alloy layer may be domain-matched epitaxially grown directly on the substrate, or may be lattice-matched epitaxially grown directly on the buffer layer. The cubic layer may also be used to form single and multiple quantum wells. Accordingly, electronic devices having wider bandgap, increased binding energy of excitons, and/or reduced density of growth and/or misfit dislocations in the active layers as compared with conventional III-nitride electronic devices may be provided.
    Type: Application
    Filed: January 15, 2002
    Publication date: July 4, 2002
    Inventors: Jagdish Narayan, Ajay Kumar Sharma, John F. Muth
  • Patent number: 5453153
    Abstract: An improved method of zone-melting recrystallizing of a silicon film on an insulator in which the film is implanted and annealed to achieve a reduction of the density of defects within the film.
    Type: Grant
    Filed: March 5, 1992
    Date of Patent: September 26, 1995
    Assignee: Kopin Corporation
    Inventors: John C. C. Fan, Paul M. Zavracky, Jagdish Narayan, Lisa P. Allen, Duy-Phach Vu, Ngwe K. Cheong
  • Patent number: 5406123
    Abstract: Epitaxial growth of films on single crystal substrates having a lattice mismatch of at least 10% through domain matching is achieved by maintaining na.sub.1 within 5% of ma.sub.2, wherein a.sub.1 is the lattice constant of the substrate, a.sub.2 is the lattice constant of the epitaxial layer and n and m are integers. The epitaxial layer can be TiN and the substrate can be Si or GaAs. For instance, epitaxial TiN films having low resistivity can be provided on (100) silicon and (100) GaAs substrates using a pulsed laser deposition method. The TiN films were characterized using X-ray diffraction (XRD), Rutherford back scattering (RBS), four-point-probe ac resistivity, high resolution transmission electron microscopy (TEM) and scanning electron microscopy (SEM) techniques. Epitaxial relationship was found to be <100> TiN aligned with <100> Si. TiN films showed 10-20% channeling yield. In the plane, four unit cells of TiN match with three unit cells of silicon with less than 4.0% misfit.
    Type: Grant
    Filed: June 11, 1992
    Date of Patent: April 11, 1995
    Assignee: Engineering Research Ctr., North Carolina State Univ.
    Inventor: Jagdish Narayan
  • Patent number: 5221411
    Abstract: Disclosed is a method for the development of diamond thin films on a non-diamond substrate. The method comprises implanting carbon ions in a lattice-plane matched or lattice matched substrate. The implanted region of the substrate is then annealed to produce a diamond thin film on the non-diamond substrate. Also disclosed are the diamond thin films on non-diamond lattice-plane matched substrates produced by this method. Preferred substrates are lattice and plane matched to diamond such as copper, a preferred implanting method is ion implantation, and a preferred annealing method is pulsed laser annealing.
    Type: Grant
    Filed: April 8, 1991
    Date of Patent: June 22, 1993
    Assignee: North Carolina State University
    Inventor: Jagdish Narayan
  • Patent number: 5208182
    Abstract: A method of forming gallium arsenide on silicon heterostructure including the use of strained layer superlattices in combination with rapid thermal annealing to achieve a reduced threading dislocation density in the epilayers. Strain energy within the superlattices causes threading dislocations to bend, preventing propagation through the superlattices to the epilayer. Rapid thermal annealing causes extensive realignment and annihilation of dislocations of opposite Burgers vectors and a further reduction of threading dislocations in the epilayer.
    Type: Grant
    Filed: November 12, 1991
    Date of Patent: May 4, 1993
    Assignee: Kopin Corporation
    Inventors: Jagdish Narayan, John C. C. Fan
  • Patent number: 5063202
    Abstract: The phase of the YBa.sub.2 Cu.sub.3 O.sub.9-.delta. having a perovskite unit cell structure of approximately the following dimensions a=3.8A, b=3.9A, and c=13.55A has been discovered and identified.
    Type: Grant
    Filed: April 27, 1990
    Date of Patent: November 5, 1991
    Assignee: Kopin Corporation
    Inventor: Jagdish Narayan
  • Patent number: 5021119
    Abstract: A method for reducing defects after zone melting and recrystallization of semiconductor films formed on an insulator over a semiconductor substrate by selectively removing portion of a first layer over the semiconductor film, amorphizing the exposed film portion and laterally regrowing the amorphized region.
    Type: Grant
    Filed: October 18, 1990
    Date of Patent: June 4, 1991
    Assignee: Kopin Corporation
    Inventors: John C.C. Fan, Paul M. Zavracky, Jagdish Narayan, Lisa P. Allen, Duy-Phach Vu
  • Patent number: 4885052
    Abstract: An improved method of zone-melting and recrystallizing of polysilicon film on an insulator over silicon is described.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: December 5, 1989
    Assignee: Kopin Corporation
    Inventors: John C. C. Fan, Paul M. Zavracky, Jagdish Narayan, Lisa P. Allen, Duy-Phach Vu
  • Patent number: 4863877
    Abstract: A method for reducing the defect and dislocation density in III-V material layers deposited on dissimilar substrates is disclosed. The method involves ion implantation of dopant materials to create amorphous regions within the layers followed by an annealing step during which the amorphous regions are recrystallized to form substantially monocrystalline regions. The wafers produced by the process are particularly well suited for optoelectronic devices.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: September 5, 1989
    Assignee: Kopin Corporation
    Inventors: John C. C. Fan, Jhang W. Lee, Jagdish Narayan
  • Patent number: 4774630
    Abstract: Apparatus for mounting a semiconductor device chip and making electrical connections thereto is disclosed. A semiconductor device chip has its backside connected to the surface of a substrate, and its upper surface includes a plurality of electrical pads across the entire surface thereof. A translator chip having a plurality of first electrical contacts disposed generally across the interior portion thereof are in electrical contact with the semiconductor device chip electrical pads, and a plurality of second electrical contacts disposed generally around the perimeter of the translator chip are electrically connected with the electrical terminals in the substrate to which the chip is attached. Heat may be removed from the semiconductor device chip through its backside via cooling channels in the substrate.
    Type: Grant
    Filed: September 30, 1985
    Date of Patent: September 27, 1988
    Assignee: Microelectronics Center of North Carolina
    Inventors: Arnold Reisman, Carlton M. Osburn, Lih-Tyng Hwang, Jagdish Narayan
  • Patent number: 4376755
    Abstract: This invention is a new process for producing refractory crystalline oxides having improved or unusual properties. The process comprises the steps of forming a doped-metal crystal of the oxide; exposing the doped crystal in a bomb to a reducing atmosphere at superatmospheric pressure and a temperature effecting precipitation of the dopant metal in the crystal lattice of the oxide but insufficient to effect net diffusion of the metal out of the lattice; and then cooling the crystal. Preferably, the cooling step is effected by quenching. The process forms colloidal precipitates of the metal in the oxide lattice. The process may be used, for example, to produce thermally stable black MgO crystalline bodies containing magnetic colloidal precipitates consisting of about 99% Ni. The Ni-containing bodies are solar-selective absorbers, having a room-temperature absorptivity of about 0.96 over virtually all of the solar-energy spectrum and exhibiting an absorption edge in the region of 2 .mu.m.
    Type: Grant
    Filed: January 29, 1982
    Date of Patent: March 15, 1983
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Jagdish Narayan, Yok Chen
  • Patent number: 4261764
    Abstract: This invention is a new method for the formation of high-quality ohmic contacts on wide-band-gap semiconducting oxides. As exemplified by the formation of an ohmic contact on n-type BaTiO.sub.3 containing a p-n junction, the invention entails depositing a film of a metallic electroding material on the BaTiO.sub.3 surface and irradiating the film with a Q-switched laser pulse effecting complete melting of the film and localized melting of the surface layer of oxide immediately underlying the film. The resulting solidified metallic contact is ohmic, has unusually low contact resistance, and is thermally stable, even at elevated temperatures. The contact does not require cleaning before attachment of any suitable electrical lead.This method is safe, rapid, reproducible, and relatively inexpensive.
    Type: Grant
    Filed: October 1, 1979
    Date of Patent: April 14, 1981
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventor: Jagdish Narayan
  • Patent number: 4181538
    Abstract: This invention is a method for improving the electrical properties of silicon semiconductor material. The method comprises irradiating a selected surface layer of the semiconductor material with high-power laser pulses characterized by a special combination of wavelength, energy level, and duration. The combination effects melting of the layer without degrading electrical properties, such as minority-carrier diffusion length. The method is applicable to improving the electrical properties of n- and p-type silicon which is to be doped to form an electrical junction therein. Another important application of the method is the virtually complete removal of doping-induced defects from ion-implanted or diffusion-doped silicon substrates.
    Type: Grant
    Filed: September 26, 1978
    Date of Patent: January 1, 1980
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Jagdish Narayan, Clark W. White, Rosa T. Young
  • Patent number: 4147563
    Abstract: This invention is an improved method for preparing p-n junction devices, such as diodes and solar cells. High-quality junctions are prepared by effecting laser-diffusion of a selected dopant into silicon by means of laser pulses having a wavelength of from about 0.3 to 1.1 .mu.m, an energy area density of from about 1.0 to 2.0 J/cm.sup.2, and a duration of from about 20 to 60 nanoseconds. Initially, the dopant is deposited on the silicon as a superficial layer, preferably one having a thickness in the range of from about 50 to 100 A. Depending on the application, the values for the above-mentioned pulse parameters are selected to produce melting of the silicon to depths in the range from about 1000 A to 1 .mu.m. The invention has been used to produce solar cells having a one-sun conversion efficiency of 10.6%, these cells having no antireflective coating or back-surface fields.
    Type: Grant
    Filed: August 9, 1978
    Date of Patent: April 3, 1979
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Jagdish Narayan, Rosa T. Young