Patents by Inventor Jaikwang Kim

Jaikwang Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11209709
    Abstract: A display substrate and a method thereof, a display panel and a display device are provided. The display substrate includes: a base substrate; and at least one first signal line and a first insulating layer which are disposed on the base substrate; a surface of the first insulating layer away from the base substrate and a surface of the at least one first signal line away from the base substrate are parallel with the base substrate and are substantially located in a continuous flat plane. The first insulating layer which is disposed side by side with the first signal line can improve the surface flatness level of the display substrate and prevent the subsequently formed structures on the display substrate suffering from display defectives due to a too large step.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: December 28, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaochen Cui, Peng Li, Jungho Park, Jaikwang Kim, Zhe Li, Xiaoji Li, Dongxing Zhao
  • Publication number: 20210191211
    Abstract: A display substrate and a method thereof, a display panel and a display device are provided. The display substrate includes: a base substrate; and at least one first signal line and a first insulating layer which are disposed on the base substrate; a surface of the first insulating layer away from the base substrate and a surface of the at least one first signal line away from the base substrate are parallel with the base substrate and are substantially located in a continuous flat plane. The first insulating layer which is disposed side by side with the first signal line can improve the surface flatness level of the display substrate and prevent the subsequently formed structures on the display substrate suffering from display defectives due to a too large step.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 24, 2021
    Inventors: Xiaochen CUI, Peng LI, Jungho PARK, Jaikwang KIM, Zhe LI, Xiaoji LI, Dongxing ZHAO
  • Patent number: 10916178
    Abstract: A Gate Driver on Array circuit and a driving method thereof, and a display device. The Gate Driver on Array circuit includes at least one group of shift registers, each group of shift registers includes a plurality of shift registers in cascade, the plurality of shift registers including a first shift register, a second shift register connected after the first shift register, and a third shift register connected after the second shift register, wherein the third shift register is provided with an initializing terminal connected to an output terminal of the first shift register.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: February 9, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO. LTD.
    Inventors: Yajie Bai, Zhuo Xu, Yuanbo Zhang, Yan Fang, Ming Deng, Zijie Tang, Jaikwang Kim
  • Patent number: 10831057
    Abstract: A color filter substrate, a display panel and a display device are disclosed. The color filter substrate includes a base substrate, and a color filter layer and a phase inversion pattern which are disposed on the base substrate, wherein the phase inversion pattern includes a plurality of openings corresponding to a plurality of color filter units of the color filter layer, and the phase inversion pattern defines a boundary of each of the color filter units; a projection of the phase inversion pattern on the base substrate at least partially covers a projection of an area between adjacent color filter units on the base substrate; the phase inversion pattern is configured to allow light passing through the phase inversion pattern to undergo phase inversion.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: November 10, 2020
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Peng Jiang, Liangliang Jiang, Weihua Jia, Haipeng Yang, Jaikwang Kim, Yongjun Yoon
  • Patent number: 10816842
    Abstract: An array substrate, a method for manufacturing the same, a liquid crystal display panel, and a display device are provided. The array substrate includes a first substrate, signal lines and an insulating layer; the insulating layer is disposed on the first substrate, and grooves are disposed on a side of the insulating layer facing away from the first substrate and disposed in a region of the insulating layer corresponding to a non-display region of the array substrate; and the signal lines are disposed on inner walls of the grooves, a direction of the inner walls of the grooves is arranged such that at least a portion of light incident on the signal lines from a side of the first substrate facing away from the signal lines is reflected to a display region of the array substrate.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: October 27, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Peng Li, Zhe Li, Jaikwang Kim, Zhijian Qi, Keke Gu, Zhidan Sun, Xiaoji Li, Haoxiang Fan, Lan Xin, Junhong Lu, Xiaochen Cui
  • Patent number: 10777161
    Abstract: An array substrate is disclosed. The array substrate has a display area and a non-display area in the periphery of the display area, and includes a plurality of gate lines to which gate pulse signals are provided; a plurality of data lines to which data signals are provided, wherein signals on adjacent ones of the plurality of data lines have opposite polarities; a charge sharing device includes a first thin film transistor in the non-display area, a first terminal of the first thin film transistor being connected to one of two adjacent data lines among the plurality of data lines, a second terminal thereof being connected the other of the two adjacent data lines, and a gate thereof being configured to be provided with a first control signal in a blank time period between adjacent data frames so as to turn on the first thin film transistor.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 15, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhuo Xu, Yajie Bai, Xiaoyuan Wang, Rui Wang, Jaikwang Kim, Fei Shang
  • Publication number: 20200286420
    Abstract: A Gate Driver on Array circuit and a driving method thereof, and a display device. The Gate Driver on Array circuit includes at least one group of shift registers, each group of shift registers includes a plurality of shift registers in cascade, the plurality of shift registers including a first shift register, a second shift register connected after the first shift register, and a third shift register connected after the second shift register, wherein the third shift register is provided with an initializing terminal connected to an output terminal of the first shift register.
    Type: Application
    Filed: October 19, 2017
    Publication date: September 10, 2020
    Applicants: BOE Technology Group Co., Ltd., Chongqing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Yajie BAI, Zhuo XU, Yuanbo ZHANG, Yan FANG, Ming DENG, Zijie TANG, Jaikwang KIM
  • Patent number: 10768491
    Abstract: An array substrate and a manufacture method thereof, a display panel and a display device. The array substrate includes pixel units. Each pixel unit includes a pixel electrode and a common electrode, which are respectively includes first pixel electrode strips and first common electrode strips that are arranged substantially in parallel in parallel in a first direction, each first common electrode strip overlaps at least one first pixel electrode strip. Each pixel unit includes at least one pixel unit sub-area, which has a sub-area symmetry axis, the first pixel electrode strip and the first common electrode strip are respectively arranged with respect to the sub-area symmetry axis symmetrically. On either side of the sub-area symmetry axis, the first common electrode strip is farther away from or closer to the sub-area symmetry axis than the at least one first pixel electrode strip that the each first common electrode strip overlaps.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: September 8, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Peng Li, Jungho Park, Heecheol Kim, Jaikwang Kim
  • Publication number: 20200201108
    Abstract: An array substrate, a method for manufacturing the same, a liquid crystal display panel, and a display device are provided. The array substrate includes a first substrate; signal lines and an insulating layer; the insulating layer is disposed on the first substrate, and grooves are disposed on a side of the insulating layer facing away from the first substrate and disposed in a region of the insulating layer corresponding to a non-display region of the arm substrate; and the signal lines are disposed on inner walls of the grooves, a direction of the inner walls of the grooves is arranged such that at least a portion of light incident on the signal lines from a side of the first substrate facing away from the signal lines is reflected to a display region of the array substrate.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 25, 2020
    Inventors: Peng Li, Zhe LI, Jaikwang KIM, Zhijian QI, Keke GU, Zhidan SUN, Xiaoji LI, Haoxiang FAN, Lan XIN, Junhong LU, Xiaochen CUI
  • Publication number: 20200082779
    Abstract: An array substrate is disclosed. The array substrate has a display area and a non-display area in the periphery of the display area, and includes a plurality of gate lines to which gate pulse signals are provided; a plurality of data lines to which data signals are provided, wherein signals on adjacent ones of the plurality of data lines have opposite polarities; a charge sharing device includes a first thin film transistor in the non-display area, a first terminal of the first thin film transistor being connected to one of two adjacent data lines among the plurality of data lines, a second terminal thereof being connected the other of the two adjacent data lines, and a gate thereof being configured to be provided with a first control signal in a blank time period between adjacent data frames so as to turn on the first thin film transistor.
    Type: Application
    Filed: June 30, 2017
    Publication date: March 12, 2020
    Inventors: Zhuo XU, Yajie BAI, Xiaoyuan WANG, Rui WANG, Jaikwang KIM, Fei SHANG
  • Patent number: 10541257
    Abstract: The disclosure discloses an array substrate, a display panel and a display device. The array substrate includes a peripheral circuit area in which a plurality of first wire grooves, a plurality of second wire grooves, a plurality of first lead wires and a plurality of second lead wires are arranged, wherein each first lead wire is arranged corresponding to one of the first wire grooves, and laid out on a bottom and sidewalls of a corresponding first wire groove; and each second lead wire is arranged corresponding to one of the second wire grooves, and a plurality of recesses and protrusions are arranged alternately on a bottom surface of each second wire groove along an extension direction of the each second wire groove, wherein each second lead wire is laid out on surfaces of recesses and protrusions on a bottom surface of a corresponding second wire groove.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: January 21, 2020
    Assignees: BOE Technology Group Co., Ltd., Chongqing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Peng Li, Zhe Li, Xiaoji Li, Jaikwang Kim, Keke Gu, Lan Xin
  • Publication number: 20190361301
    Abstract: An array substrate and a manufacture method thereof, a display panel and a display device. The array substrate includes pixel units. Each pixel unit includes a pixel electrode and a common electrode, which are respectively includes first pixel electrode strips and first common electrode strips that are arranged substantially in parallel in parallel in a first direction, each first common electrode strip overlaps at least one first pixel electrode strip. Each pixel unit includes at least one pixel unit sub-area, which has a sub-area symmetry axis, the first pixel electrode strip and the first common electrode strip are respectively arranged with respect to the sub-area symmetry axis symmetrically. On either side of the sub-area symmetry axis, the first common electrode strip is farther away from or closer to the sub-area symmetry axis than the at least one first pixel electrode strip that the each first common electrode strip overlaps.
    Type: Application
    Filed: August 2, 2017
    Publication date: November 28, 2019
    Inventors: Peng LI, Jungho PARK, Heecheol KIM, Jaikwang KIM
  • Patent number: 10429702
    Abstract: The present disclosure provides a pixel structure, an array substrate and a display apparatus, aiming at achieving good display effects in all viewing directions and improved viewing angles. The pixel structure comprises a plurality of transparent electrodes, which are arranged in columns and each transparent electrode corresponds to a subpixel. Each transparent electrode comprises at least two sub-electrode portions, and each sub-electrode portion is provided with a plurality of slits.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: October 1, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Rui Wang, Haijun Qiu, Fei Shang, Jaikwang Kim, Shaoru Li, Rikun Jiang
  • Patent number: 10424604
    Abstract: The present disclosure provides an array substrate, its manufacturing method, and a display apparatus containing the array substrate. The array substrate includes: a substrate; a plurality of gate lines and a plurality of data lines, disposed over the substrate and arranged in rows and columns respectively; and a plurality of pixel regions, each arranged in an area defined by crossing gate lines and data lines and comprising a pixel electrode. The plurality of data lines are configured such that in each pixel region, orthographic projection of any one of the plurality of data lines on the substrate and orthographic projection of a corresponding pixel electrode on the substrate has an overlapping area having a width of ?0 ?m.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: September 24, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Rui Wang, Haijun Qiu, Fei Shang, Jaikwang Kim, Shaoru Li, Zhuo Xu
  • Patent number: 10417979
    Abstract: An array substrate, a display panel and a driving method thereof. The array substrate includes a plurality of right-angled triangular subpixels. Each subpixel and another adjacent subpixel form a corresponding rectangular virtual pixel, and the plurality of subpixels form a plurality of virtual pixels arranged in an array. Every four adjacent subpixels which belong to different virtual pixels respectively form a corresponding diamond-shaped physical pixel.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: September 17, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhuo Xu, Yajie Bai, Xing Xiong, Jaikwang Kim, Fei Shang, Wu Wang
  • Patent number: 10311811
    Abstract: The array substrate comprises a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction crossing the first direction, and a plurality of pixel units arranged as an array. Each of the plurality of data lines is arranged between two columns of pixel units, the two columns of the pixel units extending in the second direction and being adjacent to each other in the first direction, and the data line is connected to pixel units at one side of said data line or to pixel units at the other side of said data line. Each of the plurality of data lines switches the direction of connection from one side to the other in an alternating manner with each two adjacent rows of pixel units, and the plurality of data lines have the same connection direction in each row of pixel units.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: June 4, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaoyuan Wang, Wu Wang, Jaikwang Kim, Zhuo Xu, Yajie Bai
  • Patent number: 10297218
    Abstract: The present application discloses an array substrate, a driving method thereof, and related display apparatus based on an improved dual-gate scheme. The array substrate includes multiple groups each having two columns of pixel electrodes without laying a data line in a gap between the two columns. Each group includes multiple second transistors for pre-charging respective pairs of pixel electrodes having reversed polarities in each corresponding scanning cycle. Before each pixel electrode is charged via a first transistor, turning on the second transistor allows charge sharing between the two pixel electrodes having reversed polarities so that the charging time of each pixel electrodes is substantially reduced and the operation power is saved.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 21, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Chongqing BOE Optoelectronics Technology CO., Ltd.
    Inventors: Zhuo Xu, Rui Wang, Yajie Bai, Jaikwang Kim, Fei Shang, Haijun Qiu
  • Patent number: 10263017
    Abstract: A pixel structure, a display panel and a manufacturing method of the pixel structure are disclosed. The pixel structure includes: gate lines extending in parallel in a first direction; data lines extending in parallel in a second direction; and a plurality of pixel units defined by the gate lines and the data lines. One of the data lines is disposed between two pixel units which are adjacent to each other in the first direction, and two of the gate lines are disposed between two pixel units which are adjacent to each other in the second direction. Each of the pixel units comprises two pixel regions which are arranged side by side in the first direction, each of the pixel regions comprises a pixel electrode, and each of the pixel units comprises a unitary common electrode which covers the two pixel regions.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: April 16, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Weihua Jia, Haipeng Yang, Jaikwang Kim, Yongjun Yoon
  • Publication number: 20190094634
    Abstract: The present disclosure provides a pixel structure, an array substrate and a display apparatus, aiming at achieving good display effects in all viewing directions and improved viewing angles. The pixel structure comprises a plurality of transparent electrodes, which are arranged in columns and each transparent electrode corresponds to a subpixel. Each transparent electrode comprises at least two sub-electrode portions, and each sub-electrode portion is provided with a plurality of slits.
    Type: Application
    Filed: October 11, 2016
    Publication date: March 28, 2019
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Rui WANG, Haijun QIU, Fei SHANG, Jaikwang KIM, Shaoru LI, Rikun JIANG
  • Publication number: 20190067330
    Abstract: The disclosure discloses an array substrate, a display panel and a display device. The array substrate includes a peripheral circuit area in which a plurality of first wire grooves, a plurality of second wire grooves, a plurality of first lead wires and a plurality of second lead wires are arranged, wherein each first lead wire is arranged corresponding to one of the first wire grooves, and laid out on a bottom and sidewalls of a corresponding first wire groove; and each second lead wire is arranged corresponding to one of the second wire grooves, and a plurality of recesses and protrusions are arranged alternately on a bottom surface of each second wire groove along an extension direction of the each second wire groove, wherein each second lead wire is laid out on surfaces of recesses and protrusions on a bottom surface of a corresponding second wire groove.
    Type: Application
    Filed: June 11, 2018
    Publication date: February 28, 2019
    Inventors: Peng LI, Zhe LI, Xiaoji LI, Jaikwang KIM, Keke GU, Lan XIN