Abstract: An apparatus for incorporating a metallic foil into a semiconductor package includes a carrier embossed with a multiplicity of cavities. Each of the cavities define a pedestal recessed with the cavities which penetrate only partially through the thickness of the carrier. A metallic foil overlying a pattern with the pedestals in direct contact and help support the metallic foil with the metallic foil pressed into at least some of the cavities. In other embodiments, a gap is between the metallic foil and bottoms of the cavities in a substrate. Integrated circuit dice are attached to the foil. Each die is attached to the foil in a region of the foil overlying a portion of the at least one device area pattern. Bonding wires electrically connect the integrated circuit dice to the foil.

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converter packages and other devices using stacked leadframes.

Abstract: Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution.

Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Abstract: A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads.

Abstract: A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 ?m to about 35 ?m.

Abstract: Apparatuses and methods directed to a semiconductor chip package having multiple leadframes are disclosed. Packages can include a first leadframe having a die attach pad and a first plurality of electrical leads, a second leadframe that is generally parallel to the first leadframe and having a second plurality of electrical leads, and a plurality of direct electrical connectors between the first and second leadframes, where such direct electrical connectors control the distance between the leadframes. Additional device components can include a primary die, an encapsulant, a secondary die, an inductor and/or a capacitor. The plurality of direct electrical connectors can comprise polymer balls having solder disposed thereabout. Alternatively, the direct electrical connectors can comprise metal tabs that extend from one leadframe to the other. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converter packages and other devices using stacked leadframes.

Abstract: The present inventions relate generally to methods for packaging integrated circuits using thin foils that form electrical interconnects for the package. The foil includes a base layer (such as copper) with an optional plating layer (such as silver) suitable for improving adhesion of the bonding wires (or other connectors) to the foil. The base layer (or the plated surface if the foil is preplated) of the foil is patterned by laser ablation to define components (e.g. contacts) of a device area. The patterning is arranged to ablate entirely through selected portions of the plating layer and part, but not all, of the way through corresponding underlying portions of the base layer. In some embodiments, the metallic foil is partially etched after the laser ablation in order to deepen the trenches that define the patterning of the foil. Multiple dice may then be attached to die attach pad areas of the plated foil and electrically coupled to electrical contacts.

Abstract: A variety of improved arrangements and processes for packaging integrated circuits are described. More particularly, methods of encapsulating dice in lead frame based IC packages are described that facilitate covering some portions of the bottom surface of the lead frame while leaving other portions of the bottom surface of the lead frame exposed. In some embodiments, a method of encapsulating integrated circuits mounted on a lead frame panel is described. The lead frame panel includes a plurality of leads having associated contacts and supports. A shim having a plurality of cavities is positioned under the lead frame such that the cavities are adjacent to the supports and not adjacent to the contacts. During the encapsulation process, encapsulant material flows under the supports such that the bottom surfaces of the supports are electrically insulated by the encapsulant while the bottom surfaces of the contacts remain exposed.

Abstract: A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads.

Abstract: Apparatuses and methods directed to a semiconductor chip package having multiple leadframes are disclosed. Packages can include a first leadframe having a die attach pad and a first plurality of electrical leads, a second leadframe that is generally parallel to the first leadframe and having a second plurality of electrical leads, and a plurality of direct electrical connectors between the first and second leadframes, where such direct electrical connectors control the distance between the leadframes. Additional device components can include a primary die, an encapsulant, a secondary die, an inductor and/or a capacitor. The plurality of direct electrical connectors can comprise polymer balls having solder disposed thereabout. Alternatively, the direct electrical connectors can comprise metal tabs that extend from one leadframe to the other. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.

Abstract: An integrated circuit package is described that includes an integrated circuit die, a plurality of lower contact leads, and an insulating substrate positioned over the die and lower contact leads. The insulating substrate includes a plurality of electrically conducting upper routing traces formed on the bottom surface of the substrate. The traces on the bottom surface of the substrate electrically couple each lower contact lead with an associated I/O pad.

Abstract: Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution.

Abstract: A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 ?m to about 35 ?m.

Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.

Abstract: Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material.