Patents by Inventor Jaime A. Bayan
Jaime A. Bayan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7045035Abstract: A post singulation, die separation assembly for bulk separation of a plurality of dice in a singulated wafer from the adhesive backing of wafer saw tape. The die separation assembly includes a support base having a support surface. A feed tray includes a collection end positioned adjacent the base such that an elongated, substantially tin gap is formed between the tray collection end and at least a portion of the base. A flexible platform is movably supported atop the base support surface for movement along the base. Upon movement of the flexible platform down the down-ramped portion of the support base, a portion of the wafer saw tape thereat is peeled away from the respective die. The tape is the separated from the dice, releasing the respective dice onto the collection end of the feed tray in a manner substantially maintaining their forward alignment orientation of thereof.Type: GrantFiled: April 6, 2005Date of Patent: May 16, 2006Assignee: National Semiconductor CorporationInventors: Nikhil Kelkar, Ken Pham, Jaime A. Bayan, Cheol Hyun Han
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Patent number: 7023074Abstract: Methods of fabricating leadless packages are described that provide good solder joint reliability. In most respects, the packages are fabricated in a manner similar to current lead frame based leadless packaging techniques. However, at some point in the process, the contacts are provided with undercut regions that are left exposed during solder plating so that the solder plating also covers the exposed side and undercut segments of the contacts. When the resultant devices are soldered to an appropriate substrate (after singulation), each resulting solder joint includes a fillet that adheres very well to the undercut portion of contact. This provides a high quality solder joint that can be visually inspected from the side of the package.Type: GrantFiled: January 3, 2005Date of Patent: April 4, 2006Assignee: National Semiconductor CorporationInventors: Felix C. Li, Jaime A. Bayan, Santhiran Nadarajah, Ah Lek Hu
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Patent number: 6932136Abstract: A post singulation, die separation assembly for bulk separation of a plurality of dice in a singulated wafer from the adhesive backing of wafer saw tape. The die separation assembly includes a support base having a support surface, a first portion and an opposite second portion thereof. The second portion includes a down-ramped portion thereof skewed downwardly at a first acute angle from the support surface. A feed tray includes a collection end positioned adjacent the base second portion such that an elongated, substantially thin gap is formed between the tray collection end and at least a portion of the base second portion. A flexible platform is movably supported atop the base support surface for movement from the first portion to the second portion thereof. At the second portion, the platform passes downward through the gap formed between the tray collection end and the at least a portion of the base second portion.Type: GrantFiled: April 8, 2004Date of Patent: August 23, 2005Assignee: National Semiconductor CorporationInventors: Nikhil Kelkar, Ken Pham, Jaime A. Bayan, Cheol Hyun Han
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Patent number: 6930377Abstract: A number of apparatus for packaging semiconductor devices using an epoxy ink or adhesive. In one embodiment, a pattern of epoxy is formed on the bottom surface of die attach pad of a leadless semiconductor package. The pattern of epoxy divides the undersurface of the die attach pad into a grid of small squares. A small amount of solder paste is then applied within each square of the grid. When the leadless package is attached to a substrate, each of the solder balls evenly reflows to the same approximate height. This enhances the attachment of the package to the substrate and reduces the need for rework. In another embodiment, a protective layer of epoxy or ink is provided around the periphery of the die after it has been attached to the die attach pad. The protective layer covers any solder material that may leach out from between the die and the die attach pad. In another embodiment, a protective layer of epoxy or ink is provided on the exposed tie bars of the lead frame after encapsulation.Type: GrantFiled: December 4, 2002Date of Patent: August 16, 2005Assignee: National Semiconductor CorporationInventor: Jaime A. Bayan
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Patent number: 6872599Abstract: Methods of fabricating leadless packages are described that provide good solder joint reliability. In most respects, the packages are fabricated in a manner similar to current lead frame based leadless packaging techniques. However, at some point in the process, the contacts are provided with undercut regions that are left exposed during solder plating so that the solder plating also covers the exposed side and undercut segments of the contacts. When the resultant devices are soldered to an appropriate substrate (after singulation), each resulting solder joint includes a fillet that adheres very well to the undercut portion of contact. This provides a high quality solder joint that can be visually inspected from the side of the package.Type: GrantFiled: December 10, 2002Date of Patent: March 29, 2005Assignee: National Semiconductor CorporationInventors: Felix C. Li, Jaime A. Bayan, Santhiran Nadarajah, Ah Lek Hu
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Patent number: 6797540Abstract: Methods of fabricating leadless packages are described that facilitate increased contact density. Each device area in a lead frame panel has a die attach pad and a multiplicity of conductive contacts. The contacts are carried by tie bars and the die attach pad is carried by support bars that extend from the contacts. During assembly, the lead frame panel is held in position while the die attach pad support bars are severed. Once the die attach pad support bars are severed, an adhesive tape is adhered to the bottom surface of the lead frame panel so that the die attach pad may be held in position relative to its associated contacts. After the adhesive tape has been applied, the leadless packages may be assembled in a conventional manner.Type: GrantFiled: November 18, 2002Date of Patent: September 28, 2004Assignee: National Semiconductor CorporationInventors: Felix D. Li, Jaime A. Bayan
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Patent number: 6781243Abstract: A semiconductor package is provided with an internal package formed in the cavity of the external leadless leadframe package (LLP). The internal package is a leadless leadframe package and provides a substrate for mounting one or more die and passive devices to form the external LLP. By arranging the die and passive components on the internal package, higher chip density and a smaller form factor may be achieved.Type: GrantFiled: January 22, 2003Date of Patent: August 24, 2004Assignee: National Semiconductor CorporationInventors: Felix C. Li, Jaime A. Bayan
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Patent number: 6777788Abstract: Embodiments of the invention include an integrated circuit package and methods for its construction. An integrated circuit package of the invention includes a die attach pad and a plurality of lead pads. An integrated circuit die is mounted with the front side of the die attach pad and electrically connected to the plurality of lead pads. Additionally, the backside of the die attach pad includes a pattern of mesas formed thereon. Each of the mesas is configured such that they have a top surface area that is substantially the same size as the surface area of the lead pads. A contact layer of reflowable material is formed on the top surface of the mesas and the lead pads, forming an integrated circuit package with an improved contact layer.Type: GrantFiled: September 10, 2002Date of Patent: August 17, 2004Assignee: National Semiconductor CorporationInventors: Sharon Ko Mei Wan, Jaime A. Bayan
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Patent number: 6483180Abstract: A semiconductor device exhibiting a lower incidence of burrs forming on its contacts during the singulation process. The semiconductor device includes a die which is electrically connected to a set of contacts wherein each contact has a contact surface and a non-contact surface. Each contact surface of the contacts contains a recessed region filled with a first deposit of molding material. The die and the non-contact surfaces of the contacts are encapsulated with a second deposit of molding material. The semiconductor device is singulated from a molded lead frame by guiding a saw blade through recessed regions formed on the contact surface of the contacts. The molding material in the recessed regions creates a “buffer zone” which separates the path of the saw blade from the contact surface of the contacts.Type: GrantFiled: December 23, 1999Date of Patent: November 19, 2002Assignee: National Semiconductor CorporationInventors: Jaime A. Bayan, Peter Howard Spalding
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Patent number: 6364089Abstract: The invention relates to apparatus and methods for semiconductor device handling. In one aspect, the invention relates to a rotary flipper including a wheel having a plurality of stations. A semiconductor device is placed within a first station in a first orientation. While the semiconductor device is held, the wheel portion of the rotary flipper rotates and the next station receives another semiconductor device. When the first station is in an unloading position, the semiconductor device is released. At this point, the semiconductor device is oriented in a second position. In one aspect, the semiconductor device is released into a cavity of a tape and reel. In another aspect, vacuum pressure is applied to hold the die. In one embodiment, the invention relates to a semiconductor device handling apparatus and apparatus that includes of a rotary semiconductor device flipper.Type: GrantFiled: December 10, 1999Date of Patent: April 2, 2002Assignee: National Semiconductor CorporationInventors: Inderjit Singh, Jaime A. Bayan, Hem Takiar, Ashok S. Prabhu
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Patent number: 6001723Abstract: A method of forming an interconnection contact for integrated circuit package components includes providing an integrated circuit package component having a contact pad on which the interconnecting contact is to be formed. The interconnecting contact is formed by forming at least a portion of a bonding wire loop connected to the contact pad. A first end of a bonding wire is connected to the contact pad. The bonding wire loop includes a wire portion extending outwardly from the contact pad. The portion of the bonding wire loop forms the interconnection contact for electrically connecting the integrated circuit package component to other electrical devices. In one embodiment, a second end of the bonding wire loop is connected to the same contact pad that the first end of the bonding wire loop is connected to. In another embodiment, a second end of the bonding wire loop is connected to another contact pad.Type: GrantFiled: December 24, 1997Date of Patent: December 14, 1999Assignee: National Semiconductor CorporationInventors: Nikhil Kelkar, Jaime A. Bayan
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Patent number: 5780772Abstract: A method of preventing non-uniform bonding wire sweep during an encapsulating process of an integrated circuit package includes the step of forming an encapsulating material flow restricting element between two widely spaced functional bonding wires. The integrated circuit package includes an array of electrically conductive leads for electrically connecting the package to other electrical elements and an integrated circuit die having a plurality of input/output terminal pads. A plurality of functional bonding wires electrically connects certain ones of the input/output terminal pads to associated electrically conductive leads such that the functional bonding wires have a predetermined pitch which defines an approximate minimum desired spacing between adjacent functional bonding wires. The plurality of functional bonding wires includes two widely spaced functional bonding wires which are spaced apart from one another by a distance substantially greater than the predetermined minimum desired spacing.Type: GrantFiled: January 24, 1997Date of Patent: July 14, 1998Assignee: National Semiconductor CorporationInventors: Inderjit Singh, Jaime A. Bayan
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Patent number: 5569956Abstract: An interposer between the leads of a leadframe and the ends of wires connected to an integrated circuit die is described herein. The interposer may consist a polyimide tape or other insulating material with conductive traces formed thereon, each trace electrically connecting an inner bonding pad to an outer bonding pad formed on the tape. The outer bonding pads are generally arranged around the periphery of the interposer and are bonded to respective ends of the leadframe. An integrated circuit die is placed in approximately the center of the interposer surrounded by the inner bonding pads. An automatic bonder then bonds wires to the bonding pads on the die and to the inner bonding pads on the interposer. The die is now electrically connected to the leadframe via the traces on the interposer.Type: GrantFiled: August 31, 1995Date of Patent: October 29, 1996Assignee: National Semiconductor CorporationInventors: Satya N. Chillara, Jaime A. Bayan
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Patent number: 5146310Abstract: A thermally enhanced leadframe having heat conductive paths which thermally couple a die attach pad to thermal connection points spread out as far as possible from each other on the perimeter of the package. The area of the heat conductive path is maximized to occupy substantially all area in the package not occupied by the electrically conductive paths between the wire bond locations and the external connection points such as pins. This configuration maximizes the area of the printed circuit board which is heated thereby increasing thermal cooling efficiency. Further, the leadframe configuration maximizes the area of contact between the integrated circuit package and the heat conductive path thereby increasing the thermal conductivity between the device junctions on the integrated circuit die and the ambient through the material of the package itself.Type: GrantFiled: July 18, 1991Date of Patent: September 8, 1992Assignee: National Semiconductor Corp.Inventors: Jaime A. Bayan, Jeffrey C. Demmin, Mark L. DiOrio, Young I. Kwon