Patents by Inventor Jam-Wem Lee

Jam-Wem Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching
    Patent number: 9887275
    Abstract: A method of forming an integrated circuit device includes forming a gate stack covering a middle portion of a semiconductor fin, forming a gate spacer layer over the gate stack and the semiconductor fin, and patterning the gate spacer layer. The resulting spacers include a gate spacer on a sidewall of the gate stack, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer is then etched. When the etching is finished, a height of the fin spacer is smaller than about a half of the height of the semiconductor fin.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Tsung-Che Tsai, Yi-Feng Chang
  • Double Sided NMOS/PMOS Structure and Methods of Forming the Same
    Publication number: 20170352598
    Abstract: A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Inventor: Jam-Wem Lee
  • ESD Protection Device
    Publication number: 20170346277
    Abstract: Systems and methods for protecting a device from an electrostatic discharge (ESD) event are provided. A resistor-capacitor (RC) trigger circuit and a driver circuit are provided. The RC trigger circuit is configured to provide an ESD protection signal to the driver circuit. A discharge circuit includes a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential. The driver circuit provides one or more signals for turning the first and second MOS transistors on and off.
    Type: Application
    Filed: December 2, 2016
    Publication date: November 30, 2017
    Inventors: Shu-Yu Su, Jam-Wem Lee, Wun-Jie Lin
  • Dynamic threshold MOS and methods of forming the same
    Patent number: 9818842
    Abstract: A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Multi-gate high voltage device
    Patent number: 9768164
    Abstract: A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • SEMICONDUCTOR ARRANGEMENT FACILITATING ENHANCED THERMO-CONDUCTION
    Publication number: 20170256530
    Abstract: A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.
    Type: Application
    Filed: May 24, 2017
    Publication date: September 7, 2017
    Inventors: Ming-Hsiang SONG, Jam-Wem LEE, Yi-Feng CHANG, Wun-Jie LIN
  • Double sided NMOS/PMOS structure and methods of forming the same
    Patent number: 9754844
    Abstract: A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Backside Contacts for Integrated Circuit Devices
    Publication number: 20170207169
    Abstract: A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region.
    Type: Application
    Filed: April 5, 2017
    Publication date: July 20, 2017
    Inventor: Jam-Wem Lee
  • Semiconductor arrangement facilitating enhanced thermo-conduction
    Patent number: 9666575
    Abstract: A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ming-Hsiang Song, Jam-Wem Lee, Yi-Feng Chang, Wun-Jie Lin
  • ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR DIFFERENTIAL SIGNAL DEVICES
    Publication number: 20170125400
    Abstract: A robust electrostatic (ESD) protection device is provided. In one example, the ESD protection device is configured to accommodate three nodes. When used with a differential signal device, the first and second nodes may be coupled with the differential signal device's BP and BM signal lines, respectively, and the third node may be coupled to a voltage source. This allows for a single ESD protection device to be used to protect the signal lines of the differential signal device, thus providing significant substrate area savings as compared to the conventional means of using three dual-node ESD protection devices to accomplish substantially the same protection mechanism. Moreover, the ESD protection device may be structurally designed to handle high voltage ESD events, as required by the FlexRay standard.
    Type: Application
    Filed: May 24, 2016
    Publication date: May 4, 2017
    Inventor: JAM-WEM LEE
  • Method of Reducing the Heights of Source-Drain Sidewall Spacers of FinFETs Through Etching
    Publication number: 20170117390
    Abstract: A method of forming an integrated circuit device includes forming a gate stack covering a middle portion of a semiconductor fin, forming a gate spacer layer over the gate stack and the semiconductor fin, and patterning the gate spacer layer. The resulting spacers include a gate spacer on a sidewall of the gate stack, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer is then etched. When the etching is finished, a height of the fin spacer is smaller than about a half of the height of the semiconductor fin.
    Type: Application
    Filed: January 4, 2017
    Publication date: April 27, 2017
    Inventors: Jam-Wem Lee, Tsung-Che Tsai, Yi-Feng Chang
  • Backside contacts for integrated circuit devices
    Patent number: 9633910
    Abstract: A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Diode structure compatible with FinFET process
    Patent number: 9601627
    Abstract: An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Che Tsai, Yi-Feng Chang, Jam-Wem Lee
  • Diode formed of PMOSFET and schottky diodes
    Patent number: 9576949
    Abstract: A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Wan-Yen Lin, Ming-Hsiang Song, Cheng-Hsiung Kuo, Yue-Der Chih
  • Methods and apparatus for increased holding voltage in silicon controlled rectifiers for ESD protection
    Patent number: 9576945
    Abstract: Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Tzu-Heng Chang, Tsung-Che Tsai, Ming-Hsiang Song
  • DIODE STRING IMPLEMENTATION FOR ELECTROSTATIC DISCHARGE PROTECTION
    Publication number: 20170040311
    Abstract: A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 9, 2017
    Inventors: Tsung-Che TSAI, Jam-Wem LEE
  • Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching and the FinFETs thereof
    Patent number: 9548367
    Abstract: An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions have a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin. The semiconductor fin has a first height. The integrated circuit device further includes a gate stack over a middle portion of the semiconductor fin, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer has a second height. The first height is greater than about two times the second height.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: January 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Tsung-Che Tsai, Yi-Feng Chang
  • Dynamic Threshold MOS and Methods of Forming the Same
    Publication number: 20160372577
    Abstract: A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventor: Jam-Wem Lee
  • Diode string implementation for electrostatic discharge protection
    Patent number: 9484338
    Abstract: A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: November 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Che Tsai, Jam-Wem Lee
  • Multi-Gate High Voltage Device
    Publication number: 20160315079
    Abstract: A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors.
    Type: Application
    Filed: July 1, 2016
    Publication date: October 27, 2016
    Inventor: Jam-Wem Lee