Abstract: A transistor (10 or 11) and method of formation. The transistor (10) has a substrate (12). The substrate (12) has an overlying dielectric layer (14) and an insulated conductive control electrode (16) which overlies the dielectric layer (14). A dielectric region (18) overlies the insulated conductive control electrode (16), and a dielectric region (20) is adjacent to the insulated conductive control electrode (16). A spacer (30) is adjacent to the dielectric region (20). Epitaxial regions (24) are adjacent to the spacer (30) and the spacer (30) is overlying portions of the epitaxial regions (24). A dielectric region (26) overlies the epitaxial regions (24). Highly doped source and drain regions (32) underlie the epitaxial regions (24). LDD regions (28), which are underlying the spacer (30), are adjacent to and electrically connected to the source and drain regions (32).

Abstract: A semiconductor device having an overlapping memory cell (10), which includes a split wordline configuration and intersects at least a portion of the driver gate electrodes with each wordline. In one embodiment, a semiconductor substrate (11) has first and second active regions (13, 15) therein. A driver transistor (20) is formed in the semiconductor substrate (11), wherein the gate electrode (19) of the driver transistor (20) has a first portion overlying the second active region (15), a second portion extending beyond the first active region, and a third portion contacting the first active region (13). A wordline overlies (42) the second active region (15), wherein a first portion of the wordline forms the gate electrode of an access transistor (34) and a second portion of the wordline intersects the second portion of the driver transistor gate electrode (19) forming an overlap region (31).

Abstract: A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (16) is formed on the substrate surface and a material layer (17) doped with fluorinated boron is formed on the dielectric layer (16). A second P-type region (22), characterized by a high dopant concentration at the substrate surface and a uniform junction profile, is formed in the substrate adjacent to the first P-type region by diffusing boron atoms from the material layer (17) through the dielectric layer (16) and into the substrate (15). The second P-type region (22) has a very shallow junction depth which is closer to the substrate surface than the first P-type region.

Abstract: A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.

Abstract: A transistor is described having reduced series resistance and a reduced peak lateral electric field. The peak lateral field is reduced by forming an image charge in the surface of the substrate underlying the edges of the transistor gate electrode. The image charge is created by impregnating portions of an oxide layer overlying the source and drain regions with an impurity having the same conductivity as that of the underlying substrate. The depletion region formed in the substrate by the image charge provides a graduated electric filed in the channel preventing hot carrier injection into the gate oxide and increasing the breakdown voltage. The image charge is of an opposite conductivity to that of the substrate and is thus composed of minority carriers. The high concentration of majority carriers near the surface of the substrate lower the series resistance of the transistor thereby increasing the drive current.

Abstract: A semiconductor device having a thin-film transistor (22) and a process for making the device. The semiconductor device includes a substrate (11) having a principal surface. A gate electrode (29) overlies the principal surface and a gate dielectric layer (23) overlies the gate electrode (29). A conductive channel interface layer (25) overlies the upper surface of the gate electrode (29) and is spaced apart from the gate electrode (29) by the gate dielectric layer (23). A conductive thin-film layer (57) overlies the gate electrode (29) and forms a metallurgical contact to the channel interface layer (25). Remaining portions of the thin-film overlie the principal surface and form source and drain regions (63, 65) of the thin-film transistor (22). The thin-film source and drain regions (63, 65) are formed by placing a diffusion barrier cap (60) over the channel portion (61) of the thin-film layer (57) and introducing conductivity determining dopant into the thin-film layer (57).

Abstract: Defect-free field oxide isolation (34) is formed by oxidizing through a silicon nitride layer (30) which overlies the isolation regions (22) of the silicon substrate (12). Additionally, the silicon nitride layer (30) acts as a diffusion barrier during field growth, and thus inhibits the lateral diffusion of oxygen underneath the oxidation mask (18). Therefore, field oxide encroachment into the adjacent active regions is effectively reduced. Moreover, field oxide encroachment is also reproducibly controlled, and therefore integrated circuits with high device packing densities can be fabricated.

Abstract: A process for fabricating isolation regions in a semiconductor substrate which does not depend upon pattern definition capability. In one embodiment a device isolation region (30) is formed in a semiconductor substrate (12) by first creating a trench (18) in the substrate (12). A single-crystal SiGe layer (24) is formed to overlie the wall surface (20) of the trench (18). A layer of selectively-deposited, single-crystal silicon (26) is formed in the trench (18) using both the bottom surface (22) of the trench (18) and the SiGe layer (24) as a nucleation site for the selective deposition process. After the single-crystal silicon layer (26) is formed, the SiGe layer (24) is selectively removed and the previously occupied space is filled with a dielectric material to form isolation region (30).

Abstract: A trench is formed in a substrate and lined with a dielectric. A first silicon layer of a first conductivity is deposited in the trench. A second silicon layer of a second conductivity type is deposited over the first layer and a third silicon layer of the first conductivity type is deposited on the second layer, all are disposed within the trench area. A second trench is then formed through the third and second layers and into the first layer. The second trench is then lined with a dielectric and filled with a gate polysilicon. The appropriate connections are then made to the gate, the third layer, and the substrate.

Abstract: A transistor (10 or 11) and method of formation. The transistor (10) has a substrate (12). The substrate (12) has an overlying dielectric layer (14) and an insulated conductive control electrode (16) which overlies the dielectric layer (14). A dielectric region (18) overlies the insulated conductive control electrode (16), and a dielectric region (20) is adjacent to the insulated conductive control electrode (16). A spacer (30) is adjacent to the dielectric region (20). Epitaxial regions (24) are adjacent to the spacer (30) and the spacer (30) is overlying portions of the epitaxial regions (24). A dielectric region (26) overlies the epitaxial regions (24). Highly doped source and drain regions (32) underlie the epitaxial regions (24). LDD regions (28), which are underlying the spacer (30), are adjacent to and electrically connected to the source and drain regions (32).

Abstract: Source and drain electrodes which are overlapped and elevated with respect to an inverse-T gate electrode provide low lateral electric field, low source-drain series resistance, and uniform source and drain doping profiles while maintaining a compact layout. In one form of the invention, a semiconductor device (10) has source and drain electrodes (40) which are elevated and overlap shelf portions (21) of an inverse-T gate electrode (19). LDD regions (28) are formed in a substrate (12) and partially underlie the gate electrode. Facets (41) of the selectively deposited source and drain electrodes overlie the shelf portions of the gate electrode, thereby creating uniform doping profiles of heavily doped regions (42).

Abstract: A process for fabricating an isolated silicon on insulator (SOI) field effect transistor (FET) (10, 11, 13, 15). The SOI FET is made on a substrate material (12). In one form, a first control electrode referred to as gate (24), is contained within the substrate (12) underlying a dielectric layer (14). A second control electrode referred to as gate (26) overlies a dielectric layer (28). A source and a drain current electrode are formed from a germanium-silicon layer (18). A silicon layer (16) forms an isolated channel region of the SOI FET. The gates (12, 24) are separated from the channel by gate dielectric layers (14, 28). The germanium-silicon layer (18) is much thicker than the silicon layer (16) which is made thin to provide a thin channel region. An optional nitride layer 20 overlies the germanium-silicon layer (18).

Abstract: A semiconductor device is formed by a process in which a diffusant penetration layer and a diffusant source layer containing a boron dopant are formed overlaying the surface of a semiconductor substrate. The diffusant source layer is annealed to cause the boron dopant to controllably diffuse through the diffusant penetration layer to the semiconductor substrate to form a doped region at the surface. The diffusant source layer and the diffusant penetration layer are removed and a gate insulator is formed on the substrate surface overlaying the doped region. An N doped gate electrode is then formed overlaying the gate insulator.

Abstract: In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results ina formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.

Abstract: A stacked shared-gate CMOS transistor and method of fabrication are disclosed. An improved CMOS transistor is fabricated by the formation of a bulk transistor and an overlying isolated (SOI) transistor wherein each transistor is adjoined to a portion of a shared gate having the same conductivity type as the related transistor. The differential conductivity of the shared gate is obtained by the fabrication of a conductive diffusion-barrier layer intermediate to conductive layers. Improved switching performance is obtained as a result of higher current levels produced by the isolated transistor.

Abstract: A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of the invention a semiconductor substrate is provided having an insulating layer, a nucleating layer, and a second insulating layer overlaying the substrate. A photoresist mask is used as an implant mask and as an etch mask to expose a portion of nucleating layer. A second implant mask is formed by the selective deposition of tungsten or other material on the exposed nucleating layer. The selectively deposited material is then used to mask for a second ion implantation.

Abstract: A fully self-aligned bipolar transistor having low emitter and base-resistances is formed in a semiconductor device. In one embodiment, a patterned masking layer is formed on an active device region of a semiconductor substrate. The patterned masking layer has an opening, within which a TiN sidewall spacer is formed. The active device region is selectively doped to form an intrinsic base, using the TiN sidewall spacer and patterned masking layer as a doping mask. An emitter electrode is formed on the intrinsic base by selective deposition of silicon. An extrinsic base is also formed in the active device region by doping. Self-aligned metal silicide contacts to the extrinsic base and the emitter electrode are formed and the TiN sidewall spacer is removed.

Abstract: An insulated gate field effect device is disclosed having a channel region which includes both a horizontal and a vertical portion. The device is fabricated on a semiconductor substrate having a recess formed in its surface. The recess has a bottom forming a second surface with the wall of the recess extending between the first and second surfaces. A source region is formed at the first surface and a drain is formed at the second surface spaced apart from the wall. A channel region is defined along the wall and the second surface between the drain region and the source region. A gate insulator and gate electrode overlie the channel region.

Abstract: An improved LDD CMOS fabrication is disclosed which uses a reduced number of processing steps. In accordance with one embodiment of the invention, a silicon substrate is provided which has first and second surface regions of opposite conductivity type. First and second silicon gate electrodes overlie the first and second surface regions, respectively. A dopant source layer containing dopant impurities of the first conductivity type is deposited over the first and second gate electrodes. This dopant source layer is patterned to form sidewall spacers at the edges of the first silicon gate electrode. Those sidewall spacers are used in the formation of the LDD structure on the devices formed in the first surface region. After removing the sidewall spacers, the structure is heated to diffuse dopant impurities from the dopant source layer into the second surface region to form source and drain regions of transistors formed in that region.

Abstract: A process for the fabrication of CMOS devices is disclosed in which a selectively doped silicon layer is selectively oxidized to provide a differential thickness in the silicon and in the overlaying silicon oxide. In accordance with one embodiment, a semiconductor substrate is provided having a layer of silicon overlaying a surface of that substrate. A first area of the layer of silicon is selectively doped with N-type impurities while a second area is left undoped. The silicon is thermally oxidized to form a thermal oxide having a greater thickness over the N-type doped area than over the undoped area. Correspondingly, the silicon under the thick thermal oxide has a lesser thickness than the silicon under the thin thermal oxide. The layer of silicon is patterned to form gate electrodes and interconnects, with some of the gate electrodes formed from the silicon having N-type dopant and some of the gate electrodes formed from the silicon which is not doped N-type.