Abstract: Adjusting field effect transistor (FET) threshold voltage (V.sub.T) by diffusing impurities in polysilicon gates through a refractory metal silicide. Dopants of different conductivities may be cross-diffused. This adjustment can be made relatively late in the fabrication of the wafers to provide a quick turn around time of custom circuits, gate arrays and application specific integrated circuits (ASICs). A masking step selectively provides blocking elements to prevent the diffusion from occurring in certain of the FETs.

Abstract: A trench capacitor having increased capacitance. By means of the oxidation enhanced diffusion (OED) effect, locally outdiffused regions in the doped substrate of a semiconductor material may be formed. Thus, greater capacitance can be achieved for a trench capacitor of equal depth. This technique avoids the heretofore required extra doping in the well of opposite conductivity type that would have been necessary to prevent punchthrough if the entire lower, heavily doped region or substrate had to be formed closer to the surface of the overlying lightly doped semiconductor layer. The locally outdiffused regions may be accomplished by standard oxidation techniques.

Abstract: A method for fabricating an insulated gate field effect transistor (IGFET) having a semiconductor gate with a first portion and a second portion where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon gate of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. A semiconductor material layer, such as polycrystalline silicon (polysilicon) is selectively protected by a gate pattern mask whereby the end portions of the gates are produced by the lateral diffusion of the dopant under the edges of the gate pattern mask. Thus, the technique for defining the different portions of the gate uses other than photolithographic techniques which are limited in their resolution capabilities, and thus is readily implementable in submicron device feature processes.

Abstract: A process is disclosed for controlling the surface doping of two regions of a semiconductor device and more specifically for using such control to achieve the necessary field doping in a CMOS device structure. In accordance with one embodiment of the invention a silicon substrate is provided which has first and second regions of opposite conductivity type. A uniform doping such as by ion implantation is provided into each of the conductivity regions. The two regions or portions thereof are then simultaneously differently oxidized to cause a differential segregation of the dopant into the thermally grown oxide. The differential oxide growth can be achieved by selectively implanting halogen ions into the wafer surface prior to the thermal oxidation.

Abstract: A complementary metal-oxide-semiconductor (CMOS) isolation structure where the field isolation structure between the adjacent areas of different conductivity types has a channel stop doped with boron or phosphorus affected by germanium. The dual use of germanium and a second dopant selected from the group of phosphorus and boron provides a more precisely placed channel stop, since the germanium retards the diffusion of the boron and phosphorus and surprisingly provides improved width effect for the devices in the well where the channel stop is employed. Alternatively, the germanium may be placed in such a manner as to avoid retarding absorption of boron or phosphorus into the field oxide and retard its diffusion over the well of a different conductivity type where it is not desired.

Abstract: A process for forming an insulated gate field effect transistor (IGFET) having a semiconductor gate with a central portion and end portions on either side thereof where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon portion of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. The central portion of the gate is formed by conventional gate patterning whereas the end portions are formed by typical procedures for forming sidewall spacers using a conformal layer of in situ doped polycrystalline silicon (polysilicon) or other semiconductor material and an anisotropic etch.

Abstract: A read-only-memory circuit is disclosed which includes a plurality of column conductors and circuitry for selecting one of the plurality of column conductors in response to an input address. The selection circuitry couples each of the column conductors to a common node which is coupled to a precharge circuit such that only the selected column conductor is precharged. The precharged circuit includes first and second diode-connected IGFET devices coupled in series such that the first IGFET device is a standard enhancement mode transistor which includes an implanted channel while the second IGFET device is a natural transistor which does not include an implanted channel.

Abstract: A decoder circuit suitable for integrated circuit implementation using IGFET processing is disclosed which may be implemented in a highly dense structure. The decoder output lines are grouped in pairs and at least one of the output lines in each pair is discharged as determined by a bit in the input address. A plurality of IGFET devices under the control of the remaining input address bits selectively couple together the two output lines in each pair such that both output lines can then become discharged. Series-coupled pairs of IGFET devices are used in place of a single IGFET device in order to reduce the chip area required to implement the decoder structure.