Abstract: A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.

Abstract: An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ("SPI") that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options.

Abstract: A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.

Abstract: This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

Abstract: A polymeric film has a substrate layer of polyester material and an antistatic layer containing a polyester/polyalkylene oxide copolymer and a salt, the ratio by weight of copolymer/salt being in the range from 0.1 to 100/1. The copolymer is preferably a polyethylene terephthalate/polyethylene oxide block copolymer and the salt is preferably an alkali metal salt. The film exhibits low surface resistivity, even at low relative humidity.

Abstract: A pressure responsive dispensing pump has a hollow housing having walls forming a chamber coupled via an inlet to a supply of dispensable material. An inlet valve controls the flow of the material through the inlet into the chamber. The housing also has an outlet through which material may be discharged from the chamber under the control of a self-sealing outlet valve. At least one wall of the housing is displaceable inwardly of the chamber to reduce the volume thereof and force material out of the chamber via the outlet. The displaceable wall is connected to a flexible hinge which also moves inwardly of the chamber in response to the inward movement of the displaceable wall and thereby assists in discharging the contents of the chamber.

Abstract: This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

Abstract: This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

Abstract: A voltage switching circuit is described that includes a switching circuit for selectively coupling a first voltage to an output of the switching circuit. The first voltage has a voltage level substantially lower than zero volts. A control circuit is coupled to the switching circuit for controlling the switching circuit to couple the first voltage to the output by generating a second voltage having a voltage level lower than that of the first voltage from a third voltage having a voltage level substantially higher than zero volts.

Abstract: A magnetic novelty post card incorporating a thin sheet of magnetic material that will self-adhere to metal surfaces, and allowing an image on the front or obverse face and printed material or correspondence on the back or reverse face. A method of manufacturing a magnetic novelty post card that allows a matrix of multiple post card images to be aligned in proper registration with multiple printed paper backs, thus permitting economic and efficient use of existing post card printing plates and permitting the cutting of the multiple images into individual post cards by use of conventional die cutting or shear cutting means.

Abstract: A novel nonvolatile memory cell structure is provided using a non-self aligned CMOS process with two independent N+ implants using a two or a three polysilicon layer technology that allows in-circuit electrical erase and reprogramming together with reduction in cell size requirement. The novel memory cell is implemented with a merged transistor structure having an access transistor and a programmable transistor. The memory cell is constructed by having the control gate, formed of a first polysilicon layer, covering a portion of the channel length between drain and source to form the access portion of the merged transistors, and a floating gate formed of a second polysilicon layer overlapping a second portion of the channel length to form the programmable transistor portion of the merged transistor. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor in series with an access transistor.

Abstract: An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.

Abstract: An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.

Abstract: A nonvolatile memory residing on a single substrate is described. The nonvolatile memory includes a memory array having at least a memory cell. The memory cell includes a drain region, a source region, a control gate, and a floating gate. A drain programming voltage generation circuit is coupled to a programming voltage source and the drain region of the memory cell for providing a drain programming voltage to the drain region of the memory cell during programming of the memory cell. A control circuit is coupled to the drain programming voltage generation circuit for causing the drain programming voltage to vary with respect to a programming ability of the memory cell such that the memory cell is programmed to be within a predetermined range of a predetermined threshold voltage with a predetermined gate programming voltage for a predetermined programming time.

Abstract: A novel nonvolatile memory cell structure is provided using a non-self aligned CMOS process with two independent N+ implants using a two or a three polysilicon layer technology that allows in-circuit electrical erase and reprogramming together with reduction in cell size requirement. The novel memory cell is implemented with a merged transistor structure having an access transistor and a programmable transistor. The memory cell is constructed by having the control gate, formed of a first polysilicon layer, covering a portion of the channel length between drain and source to form the access portion of the merged transistors, and a floating gate formed of a second polysilicon layer overlapping a second portion of the channel length to form the programmable transistor portion of the merged transistor. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor in series with an access transistor.

Abstract: A method and apparatus for providing row redundancy in non-volatile semiconductor memories is disclosed. This method and apparatus provides for preconditioning of each row of memory cells prior to erasing the memory array, including any rows containing defective cells as well as any redundant rows.

Abstract: A process for removing catalyst fines from the wax product produced in a slurry Fischer-Tropsch reactor comprises removing the wax product from the reactor and separating the catalyst fines by passing the wax product through a high gradient magnetic field, whereby the catalyst fines are held by a magnetized filter element and the wax product passes through unhindered to form a purified wax product which is ready for upgrading. The separated catalyst fines are returned to the reactor by backwashing the filter element.

Abstract: This invention provides a process for converting synthesis gas to hydrocarbon fuels in the C.sub.5 -C.sub.24 (gasoline and distillate) range. The conversion proceeds with minimal formation of by-product fractions. The conversion is accomplished with a low nitrogen content iron catalyst intimately mixed with a selected zeolite.

Abstract: A methanol conversion process in which a methanol feed is catalytically converted to ethylene and gasoline over a crystalline aluminosilicate zeolite catalyst which has been presteamed in order to adjust the alpha activity of the catalyst to about 6-100. Catalyst stability and cycle time on stream are increased.

Abstract: A gaseous mixture of carbon monoxide and hydrogen is passed in contact over a first catalyst bed comprising an iron or cobalt containing Fischer-Tropsch catalyst in combination with a crystalline aluminosilicate of the class of crystalline zeolite represented by ZSM-5 so as to obtain a liquid hydrocarbon product having a boiling range of less than 400.degree. F. at a 90% overhead and being a predominantly olefinic product. The total products from said contact including said liquid hydrocarbon product are then converted over a second catalyst bed containing HZSM-5 to obtain a highly aromatic product, i.e., greater than 20 weight percent.