Abstract: A technique for generating complementary signals for joint transmission involves generating a first signal having a first wavelength and a second signal having a second wavelength. The first signal is modulated with a first modulation to encode data, and the second signal is modulated with a second modulation, which is an inverted version of the first modulation, to encode the same data such that the first and second signals are complementary. The first and second signals are combined to produce a combined signal in which power attributable to the first signal is interleaved with and substantially non-overlapping temporally with power attributable to the second signal. The combined signal is amplified and then transmitted. The first and second signals can be optical signals at respective first and second optical wavelengths, where the first and second signals are on-off keying (OOK) modulated.

Abstract: A technique for generating a data signal and a beacon signal for free space optical communications involves generating a data signal having a first optical wavelength and a beacon signal having a second optical wavelength. The data signal is encoded with data via modulation at a first modulation rate. The beacon signal is an inverted version of the data signal and can be further modulated at a second modulation rate that is less than the first modulation rate. The data and beacon signals are optically combined to produce a combined signal in which power attributable to the beacon signal is interleaved with and substantially non-overlapping temporally with power attributable to the data signal. The combined signal is amplified via a fiber amplifier, and the combined signal is supplied to transmitter optics for transmitting the data signal and the beacon signal into free space.

Abstract: A technique for simultaneously transmitting wide and narrow optical beacon signals includes generating a laser beam and splitting the laser beam into a first signal on a first path and a second signal on a second path via a wavelength-dependent beamsplitter. A wide beacon signal having a first beam divergence is generated from the first signal, and a narrow beacon signal having a second, lesser beam divergence is generated from the second signal. The wavelength of the laser beam determines an allocation of the laser energy between the wide and narrow beacon signals based on transmittance/reflectance characteristic of the beamsplitter at that wavelength. The wide and narrow beacon signals are simultaneously transmitted in a overlaid manner into free space to support acquisition and tracking in a free-space optical communication system. The beamsplitter can simultaneously transmit or reflect substantially all of a data signal at a different wavelength.

Abstract: A technique for generating a data signal and a beacon signal for free space optical communications involves generating a data signal having a first optical wavelength and a beacon signal having a second optical wavelength. The data signal is encoded with data via modulation at a first modulation rate. The beacon signal is an inverted version of the data signal and can be further modulated at a second modulation rate that is less than the first modulation rate. The data and beacon signals are optically combined to produce a combined signal in which power attributable to the beacon signal is interleaved with and substantially non-overlapping temporally with power attributable to the data signal. The combined signal is amplified via a fiber amplifier, and the combined signal is supplied to transmitter optics for transmitting the data signal and the beacon signal into free space.

Abstract: A technique for simultaneously transmitting wide and narrow optical beacon signals includes generating a laser beam and splitting the laser beam into a first signal on a first path and a second signal on a second path via a wavelength-dependent beamsplitter. A wide beacon signal having a first beam divergence is generated from the first signal, and a narrow beacon signal having a second, lesser beam divergence is generated from the second signal. The wavelength of the laser beam determines an allocation of the laser energy between the wide and narrow beacon signals based on transmittance/reflectance characteristic of the beamsplitter at that wavelength. The wide and narrow beacon signals are simultaneously transmitted in a overlaid manner into free space to support acquisition and tracking in a free-space optical communication system. The beamsplitter can simultaneously transmit or reflect substantially all of a data signal at a different wavelength.

Abstract: A valve includes a valve ball and a complex metal valve seat having a groove for receiving a low pressure seal and a convex ridge on each side of the groove. The valve ball contacts only the low pressure seal at relatively low pressures and contacts the convex ridges at relatively higher pressures to provide a metal-to-metal seal. Typically, the low pressure seal is an O-ring and the volume provided by the groove and its transition to the convex ridges is sufficient to accommodate the volume of the O-ring when the valve ball contacts the convex ridges.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: Systems and methods for providing fractional bandwidth communication channels in classes of service that do not normally support these types of channels. In one embodiment, a method comprises receiving one or more frames, wherein each frame contains non-QoS header information, classifying the one or more frames based on the corresponding non-QoS header information and scheduling delivery of the one or more frames based upon corresponding frame classifications, wherein frames in classifications corresponding to QoS circuits are scheduled in a manner that meets QoS requirements associated with the QoS circuits. When the frames are classified, they are forwarded to dynamically allocated queues corresponding to the respective classifications. Frames are scheduled for delivery from the queues according to a modified bin-filling algorithm that is designed to meet the QoS requirements of the respective circuits. This method may be implemented, for example, in a Fibre Channel Class 2 or Class 3 fabric.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: Systems and methods for providing fractional bandwidth communication channels in classes of service that do not normally support these types of channels. In one embodiment, a method comprises receiving one or more frames, wherein each frame contains non-QoS header information, classifying the one or more frames based on the corresponding non-QoS header information and scheduling delivery of the one or more frames based upon corresponding frame classifications, wherein frames in classifications corresponding to QoS circuits are scheduled in a manner that meets QoS requirements associated with the QoS circuits. When the frames are classified, they are forwarded to dynamically allocated queues corresponding to the respective classifications. Frames are scheduled for delivery from the queues according to a modified bin-filling algorithm that is designed to meet the QoS requirements of the respective circuits. This method may be implemented, for example, in a Fibre Channel Class 2 or Class 3 fabric.

Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.

Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a semiconductor substrate and including a copper portion and at least one barrier layer adjacent to the copper portion, and displacement plating surface portions of the copper portion with a plating metal more noble than copper and different than copper. The method including displacement plating provides selective and self-limiting thickness plating and enhances the electromigration resistance of the interconnect structure. The displacement plating may include subjecting the copper portion to a plating bath including the plating metal. Because displacement plating is used and is not an electroless plating process, the concentration of the metal in the aqueous plating bath and the plating time are not critical. The method may further include annealing the integrated circuit device after the displacement plating to diffuse the plating metal into the copper portion.

Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.