Abstract: In a lithographical tool utilizing off-axis illumination, masks to provide increased depth of focus and minimize CD differences between certain features is disclosed. A first mask for reducing proximity effects between isolated and densely packed features and increasing depth of focus (DOF) of isolated features is disclosed. The first mask comprises additional lines, referred to as scattering bars, disposed next to isolated edges. The bars are spaced a distance from isolated edges such that isolated and densely packed edge gradients substantially match so that proximity effects become negligible. The width of the bars set so that a maximum DOF range for the isolated feature is achieved. A second mask that is effective with quadrapole illumination only, is also disclosed. This mask "boosts" intensity levels and consequently DOF ranges for smaller square contacts so that they approximate intensity levels and DOF ranges of larger elongated contacts.

Abstract: A bipolar transistor having an emitter, a base, and a collector includes an intrinsic base region having narrow side areas and a wider central area. The side areas are located adjacent to the extrinsic base region, while the central area is disposed underneath the emitter. The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region and the central area are relatively high compared to the doping concentration of the narrow side areas of the intrinsic base. The combination of the narrow side areas and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.

Abstract: A method of printing a sub-resolution device feature having first and second edges spaced in close proximity to one another on a semiconductor substrate includes the steps of first depositing a radiation-sensitive material on the substrate, then providing a first mask image segment which corresponds to the first edge. The first mask image segment is then exposed with radiation using an imaging tool to produce a first pattern edge gradient. The first pattern edge gradient defines the first edge of the feature in the material.A second mask image segment is then provided corresponding to the second feature edge. This second mask image segment is exposed to radiation to produce a second pattern edge gradient which defines the second edge of the feature. Once the radiation-sensitive material has been developed, the two-dimensional feature is reproduced on the substrate.

Abstract: A bipolar junction transistor (BJT) which exhibits a suppressed Kirk Effect comprises a lightly-doped n-type collector region formed above a more heavily-doped n+ layer. Directly above the collector is a p-type base which has an extrinsic region disposed laterally about an intrinsic region. An n+ emitter is positioned directly above the intrinsic base region. The BJT also includes a localized n+ region disposed directly beneath the intrinsic base region which significantly increases the current handling capabilities of the transistor.

Abstract: An improved BiCMOS logic circuit utilizes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a logic reference level. Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal providing a variable load resistance. The control signal is preferably provided by a feedback network which maintains a constant voltage swing across the network over temperature.

Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates, laminated together to form a block. Each plate has a microscopic recessed portion etched into one face of the plate and a pair of holes cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

Abstract: A method of making an ultra compact laminar-flow heat exchanger includes forming microscopic regions along the front side of an elongated ribbon of material and spirally laminating the ribbon into a core wherein the front side abuts the backside of the ribbon, thereby forming enclosed microscopic channels.

Abstract: A mask for transferring square and rectangular features having critical dimensions (CDs) close to the resolution limit of the exposure tool utilized to perform the transference is described. Intensity modulation lines having the opposite transparency as the rectangular feature to be transferred, and a width significantly less than the resolution of the exposure tool, are disposed within the rectangular feature. The intensity modulation lines have the affect of damping intensity levels on the resist layer in the center of the rectangular feature. As a result, the final CD measurement of the rectangular feature is within the CD tolerance of the original designed CD measurement. In addition, since modulation lines are have dimensions well below the resolution limit of the exposure tool, they are not seen in the final rectangular resist pattern.

Abstract: An improvement for reducing proximity effects comprised of additional lines, referred to as intensity leveling bars, into the mask pattern. The leveling bars perform the function of adjusting the edge intensity gradients of isolated edges in the mask pattern, to match the edge intensity gradients of densely packed edges. Leveling bars are placed parallel to isolated edges such that intensity gradient leveling occurs on all isolated edges of the mask pattern. In addition, the leveling bars are designed to have a width significantly less than the resolution of the exposure tool. Therefore, leveling bars that are present in the mask pattern produce resist patterns that completely developed away when a nominal exposure energy is utilized during exposure of photoresist.

Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates, laminated together to form a block. Each plate has a microscopic recessed portion etched into one face of the plate and a pair of holes cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface.

Abstract: A process for fabricating a integrated circuit (IC), including a plurality of devices coupled together by a system of metal interconnects disposed above a semiconductor substrate comprises the steps of forming a plurality of conductive pedestals on the surface of the substrate. A portion of the pedestals form electrical contacts to the devices, wherein the height of the pedestals is higher than any feature of the substrate. After a polyimide layer is deposited on the substrate to a thickness which covers the pedestals, an etching step is performed until the top surface of the pedestals is coplanar with the polyimide layer. A set of metal interconnect lines is then formed over the polyimide and pedestals to form electrical connections to selected ones of the pedestal contacts.

Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface.

Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface.

Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates, laminated together to form a block. Each plate has a microscopic recessed portion etched into one face of the plate and a pair of holes cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

Abstract: A BiCMOS logic circuit utilizes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a logic reference level. Each of the bipolar transistors are resistively loaded by a p-channel metal-oxide-semiconductor (PMOS) transistor. An emitter follower, having its base coupled to the collector of one of the bipolar transistors and its collector connected to the first power supply potential, provides the output signal. NMOS transistors are used as current sources for biasing the emitter-coupled pair and the emitter follower. A circuit means provides a feedback signal coupled to the gates of the PMOS transistors for dynamically controlling the load resistance presented to said emitter coupled pair.

Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface.

Abstract: A process for faricating polysilicon resistors and polysilicon interconnects coupled to MOS field-effect devices in a silicon substrate includes the steps of depositing and etching a first polysilicon layer to form the gates of the MOS devices; then depositing a second layer of polysilicon between the gates. The second polysilicon layer is then etched so that its upper surface is substantially coplanar with the gates. Contact openings are then defined to the source, drain and gate members of the devices through an insulative layer formed over the first and second polysilicon layers. Next, a metal layer is deposited to fill the openings and is patterned to define electrical contacts to the devices. The patterning step also defines the interconnect lines in the metal layer. A third polysilicon layer is then deposited and patterned to define the polysilicon resistors and interconnects.

Abstract: An optical modulator utilizing a magnetic semiconductor device, whose operation is based on the Hall effect, includes a magnetic material formed on a semiconductor substrate. When an incoming beam of light having a dominant polarization direction is directed onto the magnetic material it becomes modulated. The result is an outgoing beam of light which has a rotated plane of polarization when compared to the dominant polarization direction. The direction of the rotated plane of polarization is indicative of the information stored in the magnetic material. The modulator of the present invention further includes a means for writing the information to the magnetic material and a semiconductor sensor means for electrically verifying the contents of the magnetic material.

Abstract: A non-volatile, static magnetic memory device, whose operation is based on the Hall effect, is disclosed. The device includes a magnetic patch which stores data in the form of a magnetic field, a semiconductor Hall bar and a pair of integrally-formed bipolar transistors used for amplifying and buffering the Hall voltage produced along the Hall bar. Current is forced to flow down the length of the Hall bar causing a Hall voltage to be developed in a direction transverse to the direction of both the magnetic field and the current. The bases of the bipolar transistors are ohmically coupled to the Hall bar to sense the Hall voltage--the polarity of which is representative of the stored information. A system of current carrying conductors is employed for writing data to individual magnetic patches.