Patents by Inventor James Allan Kahle

James Allan Kahle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9703516
    Abstract: A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.
    Type: Grant
    Filed: October 8, 2011
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle
  • Publication number: 20120030386
    Abstract: A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.
    Type: Application
    Filed: October 8, 2011
    Publication date: February 2, 2012
    Applicant: International Business Machines Corporation
    Inventors: Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle
  • Patent number: 8108564
    Abstract: A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle
  • Patent number: 8051315
    Abstract: Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: November 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: James Allan Kahle, David J. Shippy, Albert James Van Norstrand, Jr.
  • Patent number: 8032849
    Abstract: Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Harm Peter Hofstee, James Allan Kahle, Takeshi Yamazaki
  • Patent number: 8010716
    Abstract: Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: August 30, 2011
    Assignees: Sony Computer Entertainment Inc., International Business Machines Corporation
    Inventors: Takeshi Yamazaki, Scott Douglas Clark, Charles Ray Johns, James Allan Kahle
  • Publication number: 20100312969
    Abstract: Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
    Type: Application
    Filed: August 18, 2010
    Publication date: December 9, 2010
    Applicant: Sony Computer Entertainment Inc.
    Inventors: Takeshi Yamazaki, Scott Douglas Clark, Charles Ray Johns, James Allan Kahle
  • Patent number: 7814281
    Abstract: The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: October 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael Norman Day, Charles Ray Johns, James Allan Kahle, Peichum Peter Liu, Thuong Quang Truong
  • Patent number: 7802023
    Abstract: Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: September 21, 2010
    Assignees: Sony Computer Entertainment Inc., International Business Machines Corporation
    Inventors: Takeshi Yamazaki, Scott Douglas Clark, Charles Ray Johns, James Allan Kahle
  • Patent number: 7720982
    Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: May 18, 2010
    Assignees: Sony Computer Entertainment Inc., International Business Machines Corporation, Kabushiki Kaisha Toshiba
    Inventors: Masakazu Suzuoki, Takeshi Yamazaki, Harm Peter Hofstee, Martin E. Hopkins, Charles Ray Johns, James Allan Kahle, Shigehiro Asano, Atsushi Kunimatsu
  • Patent number: 7721123
    Abstract: A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: May 18, 2010
    Assignee: International Business Machines Corporation
    Inventors: Shigehiro Asano, Jeffrey Douglas Brown, Michael Norman Day, Charles Ray Johns, James Allan Kahle, Alvan Wing Ng, Michael Fan Wang, Thuong Quang Truong
  • Patent number: 7698473
    Abstract: Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: April 13, 2010
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Takeshi Yamazaki, Tsutomu Horikawa, James Allan Kahle, Charles Ray Johns, Michael Norman Day, Peichun Peter Liu
  • Patent number: 7689783
    Abstract: A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle
  • Patent number: 7657667
    Abstract: The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling the software program management of the caches. The commands include commands for writing data to the cache, loading data from the cache, and for marking data in the cache as no longer needed. The cache can be a system cache or a DMA cache.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: February 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Charles Ray Johns, James Allan Kahle, Peichun Peter Liu, Thuong Quang Truong
  • Patent number: 7650491
    Abstract: A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client forms a request, which includes the client serial number, encrypts the request with the server public key, and sends the download request to the server. The server decrypts the request with the server's private key and authenticates the client. The received client serial number is used to search for a client public key that corresponds to the embedded client private key. The server encrypts its response, which includes the requested information, with the client public key of the requesting client, and only the private key in the requesting client can be used to decrypt the information downloaded from the server.
    Type: Grant
    Filed: November 29, 2008
    Date of Patent: January 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: David John Craft, Pradeep K. Dubey, Harm Peter Hofstee, James Allan Kahle
  • Patent number: 7647433
    Abstract: A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: January 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Scott Douglas Clark, Charles Ray Johns, James Allan Kahle
  • Patent number: 7603703
    Abstract: A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client forms a request, which includes the client serial number, encrypts the request with the server public key, and sends the download request to the server. The server decrypts the request with the server's private key and authenticates the client. The received client serial number is used to search for a client public key that corresponds to the embedded client private key. The server encrypts its response, which includes the requested information, with the client public key of the requesting client, and only the private key in the requesting client can be used to decrypt the information downloaded from the server.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: October 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: David John Craft, Pradeep K. Dubey, Harm Peter Hofstee, James Allan Kahle
  • Publication number: 20090083542
    Abstract: A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client forms a request, which includes the client serial number, encrypts the request with the server public key, and sends the download request to the server. The server decrypts the request with the server's private key and authenticates the client. The received client serial number is used to search for a client public key that corresponds to the embedded client private key. The server encrypts its response, which includes the requested information, with the client public key of the requesting client, and only the private key in the requesting client can be used to decrypt the information downloaded from the server.
    Type: Application
    Filed: November 29, 2008
    Publication date: March 26, 2009
    Inventors: David John Craft, Pradeep K. Dubey, Harm Peter Hofstee, James Allan Kahle
  • Patent number: 7509457
    Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: March 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Erik Richter Altman, Peter George Capek, Michael Karl Gschwind, Charles Ray Johns, Harm Peter Hofstee, Martin E. Hopkins, James Allan Kahle, Sumedh W. Sathaye, John-David Wellman, Ravi Nair
  • Publication number: 20090070609
    Abstract: Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
    Type: Application
    Filed: November 13, 2008
    Publication date: March 12, 2009
    Inventors: James Allan Kahle, David J. Shippy, Albert James Van Norstrand, JR.