Patents by Inventor James Allan Kahle
James Allan Kahle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7062612Abstract: A system and method are provided for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is snooped. A snoop request is sent to a cache. It is determined whether the snoop request has a valid entry in the cache. Upon determining that the snoop request has a valid entry in the cache, the data is caught and sent to the cache for update.Type: GrantFiled: December 12, 2002Date of Patent: June 13, 2006Assignee: International Business Machines CorporationInventors: Jeffrey Douglas Brown, Michael Norman Day, Charles Ray Johns, James Allan Kahle, David J. Shippy, Thuong Quang Truong
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Patent number: 7010626Abstract: A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one potential load of data is predicted based on the load access pattern. In response to the prediction, the data is prefetched from a system memory to a cache before a DMA command requests the data.Type: GrantFiled: February 14, 2005Date of Patent: March 7, 2006Assignee: International Business Machines CorporationInventor: James Allan Kahle
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Patent number: 6981072Abstract: A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.Type: GrantFiled: June 5, 2003Date of Patent: December 27, 2005Assignee: International Business Machines CorporationInventors: Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle, David Shippy, Thuong Quang Truong
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Patent number: 6970982Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.Type: GrantFiled: October 1, 2003Date of Patent: November 29, 2005Assignee: International Business Machines CorporationInventors: Erik R. Altman, Peter G. Capek, Michael Karl Gschwind, Harm Peter Hofstee, James Allan Kahle, Ravi Nair, Sumedh Wasudeo Sathaye, John-David Wellman
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Patent number: 6961820Abstract: A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.Type: GrantFiled: February 12, 2003Date of Patent: November 1, 2005Assignee: International Business Machines CorporationInventors: Michael Norman Day, Charles Ray Johns, James Allan Kahle, Peichun Peter Liu, David J. Shippy, Thuong Quang Truong
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Patent number: 6931493Abstract: The present invention provides for determining an MRU or LRU way of a partitioned cache. The partitioned cache has a plurality of ways. There are a plurality of partitions, each partition comprising at least one way. An updater is employable to update a logic table as a function of an access of a way. Partition comparison logic is employable to determine whether two ways are members of the same partition, and to allow the comparison of the ways correlating to a first matrix indices and a second matrix indices. An intersection generator is employable to create an intersection box of the memory table as a function of a first and second matrix indices. Access order logic is employable to combine the output of the intersection generator, thereby determining which way is the most or least recently used way.Type: GrantFiled: January 16, 2003Date of Patent: August 16, 2005Assignee: International Business Machines CorporationInventors: Charles Ray Johns, James Allan Kahle, Peichun Peter Liu
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Patent number: 6907477Abstract: A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.Type: GrantFiled: February 19, 2004Date of Patent: June 14, 2005Assignee: International Business Machines CorporationInventors: Erik R. Altman, Peter G. Capek, Michael Gschwind, Harm Peter Hofstee, James Allan Kahle, Ravi Nair, Sumedh Wasudeo Sathaye, John-David Wellman
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Patent number: 6848044Abstract: A method of performing operations to a link stack including the step of performing a Pop operation from the link stack which includes the substeps of storing a first pointer value to the link stack, the first pointer value being the value of a pointer to the link stack before the Pop operation, and storing a first address including a first tag popped from the link stack. The method further includes the step of performing a Push operation to the link stack which includes the substeps of storing a second address including a second tag being Pushed into the link stack and storing a second pointer to the link stack, the second pointer being the value of the pointer to the link stack after the Push operation.Type: GrantFiled: March 8, 2001Date of Patent: January 25, 2005Assignee: International Business Machines CorporationInventors: Lee Evan Eisen, James Allan Kahle, Balaram Sinharoy, William John Starke
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Publication number: 20040260746Abstract: The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.Type: ApplicationFiled: June 19, 2003Publication date: December 23, 2004Applicants: International Business Machines Corporation, Sony Computer Entertainment Inc.Inventors: Jeffrey Douglas Brown, Michael Norman Day, Charles Ray Johns, James Allan Kahle, Takeshi Yamazaki
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Publication number: 20040249995Abstract: A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.Type: ApplicationFiled: June 5, 2003Publication date: December 9, 2004Applicant: International Business Machines CorporationInventors: Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle, David Shippy, Thuong Quang Truong
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Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment
Publication number: 20040236914Abstract: The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.Type: ApplicationFiled: May 22, 2003Publication date: November 25, 2004Applicant: International Business Machines CorporationInventors: Michael Norman Day, Charles Ray Johns, James Allan Kahle, Peichum Peter Liu, Thuong Quang Truong -
Patent number: 6820143Abstract: A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.Type: GrantFiled: December 17, 2002Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventors: Michael Norman Day, Charles Ray Johns, James Allan Kahle, Peichun Peter Liu, David Shippy, Thuong Quang Truong
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Publication number: 20040201970Abstract: Disclosed is an apparatus which shows the use of an inwardly disposed set of C4 type I/O connections to an integrated circuit chip over and above the typical peripherally disposed set of I/O connections which use wire type connections between the chip and other circuitry of a substrate upon which the chip is mounted. The inwardly disposed set of connections may be used to provide a direct connection to an optional ancillary chip having a corresponding set of I/O connection points. Such a construction not only increases the number of possible I/O connections, but additionally increases the bandwidth of communications between the directly connected chips.Type: ApplicationFiled: April 10, 2003Publication date: October 14, 2004Applicant: International Business Machines CorporationInventors: Paul Marlan Harvey, Harm Peter Hofstee, James Allan Kahle, Gordon J. Robbins
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Publication number: 20040193754Abstract: A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one potential load of data is predicted based on the load access pattern. In response to the prediction, the data is prefetched from a system memory to a cache before a DMA command requests the data.Type: ApplicationFiled: March 27, 2003Publication date: September 30, 2004Applicant: International Business Machines CorporationInventor: James Allan Kahle
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Patent number: 6785841Abstract: A system including a central processor and a plurality of attached processors all on a single die are disclosed. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load/store unit and logic suitable for performing a mathematical function.Type: GrantFiled: December 14, 2000Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventors: Chekib Akrout, Harm Peter Hofstee, James Allan Kahle
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Publication number: 20040162946Abstract: A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.Type: ApplicationFiled: February 13, 2003Publication date: August 19, 2004Applicant: International Business Machines CorporationInventors: Michael Norman Day, Charles Ray Johns, James Allan Kahle, Peichun Peter Liu, David J. Shippy, Thuong Quang Truong
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Publication number: 20040160835Abstract: A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.Type: ApplicationFiled: February 19, 2004Publication date: August 19, 2004Inventors: Erik R. Altman, Peter G. Capek, Michael Karl Gschwind, Harm Peter Hofstee, James Allan Kahle, Ravi Nair, Sumedh Wasudeo Sathaye, John-David Wellman
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Patent number: 6779049Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.Type: GrantFiled: December 14, 2000Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Erik R. Altman, Peter G. Capek, Michael Gschwind, Harm Peter Hofstee, James Allan Kahle, Ravi Nair, Sumedh Wasudeo Sathaye, John-David Wellman, Masakazu Suzuoki, Takeshi Yamazaki
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Publication number: 20040143706Abstract: The present invention provides for determining an MRU or LRU way of a partitioned cache. The partitioned cache has a plurality of ways. There are a plurality of partitions, each partition comprising at least one way. An updater is employable to update a logic table as a function of an access of a way. Partition comparison logic is employable to determine whether two ways are members of the same partition, and to allow the comparison of the ways correlating to a first matrix indices and a second matrix indices. An intersection generator is employable to create an intersection box of the memory table as a function of a first and second matrix indices. Access order logic is employable to combine the output of the intersection generator, thereby determining which way is the most or least recently used way.Type: ApplicationFiled: January 16, 2003Publication date: July 22, 2004Applicant: International Business Machines CorporationInventors: Charles Ray Johns, James Allan Kahle, Peichun Peter Liu
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Patent number: 6766442Abstract: A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions, a condition register, and a branch prediction circuit that predicts a condition register-dependent branch instruction by reference to a potentially stale condition register value to produce a speculative instruction fetch address. In a preferred embodiment, the processor includes branch execution circuitry that subsequently determines if the speculative instruction fetch address is correct by reference to a non-stale value of the condition register.Type: GrantFiled: March 30, 2000Date of Patent: July 20, 2004Assignee: International Business Machines CorporationInventors: James Allan Kahle, Charles Roberts Moore