Abstract: The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly coupled shared processor central processor unit (CPU). Each of the processors are generally purpose processors that have been modified by design to allow an instruction to execute and simultaneously to be stored and forwarded to shared memory operable as a trace buffer. Since each processor is general purpose, the trace routine necessary for tracing, can by one of the routines or programs that can be written and executed on either of the processors. One of the processors can run, collect and analyze the executed and store instructions of the other processor. Since the processors can be on a single chip the shared memory bus that writes and reads the executed instructions can operate at high speed.

Abstract: A data processing system including a processor having a load/store unit and a method for correcting effective address aliasing. In the load/store unit within the processor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. A real address tag is utilized to correct for effective address aliasing within the load/store unit.

Abstract: An ISYNC instruction does not cause a flush of speculatively dispatched or fetched instructions (instructions that are dispatched or fetched after the ISYNC instruction) unconditionally. The present invention detects the occurrence of any instruction that changes the state of the machine and requires a context synchronizing complete; these instructions are called context-synchronizing-required instructions. When a context-synchronizing-required instruction completes, the present invention sets a flag to note the occurrence of that condition. When an ISYNC instruction completes, the present invention causes a flush and refetches the instruction after the ISYNC if the context-synchronizing-required flag is active. The present invention then resets the context-synchronizing-required flag. If the context-synchronizing-required flag is not active, then the present invention does not generate a flush operation.

Abstract: A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client forms a request, which includes the client serial number, encrypts the request with the server public key, and sends the download request to the server. The server decrypts the request with the server's private key and authenticates the client. The received client serial number is used to search for a client public key that corresponds to the embedded client private key. The server encrypts its response, which includes the requested information, with the client public key of the requesting client, and only the private key in the requesting client can be used to decrypt the information downloaded from the server.

Abstract: A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.

Abstract: A method of performing operations to a link stack including the step of performing a Pop operation from the link stack which includes the substeps of storing a first pointer value to the link stack, the first pointer value being the value of a pointer to the link stack before the Pop operation, and storing a first address including a first tag popped from the link stack. The method further includes the step of performing a Push operation to the link stack which includes the substeps of storing a second address including a second tag being Pushed into the link stack and storing a second pointer to the link stack, the second pointer being the value of the pointer to the link stack after the Push operation.

Abstract: An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.

Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: A method of executing microprocessor instructions and an associated microprocessor are disclosed. Initially, a conditional branch instruction is fetched from a storage unit such as an instruction cache. Branch prediction information embedded in the branch instruction is detected by a fetch unit of the microprocessor. Depending upon the state of the branch prediction information, instructions from the branch-taken path and the branch-not-taken path of the branch instruction are fetched. The branch-not-taken path instructions and the branch-taken path instruction may be speculatively executed. Upon executing the conditional branch instruction, the speculative results from the branch-taken path are discarded if the branch is not taken and speculative results from the branch-not-taken path are discarded if the branch is taken. The branch prediction information may include compiler generated information indicative of the context in which the conditional branch instruction is used.

Abstract: A method and system for atomic memory accesses in a processor system, wherein the processor system is able to issue and execute multiple instructions out of order with respect to a particular program order. A first reservation instruction is speculatively issued to an execution unit of the processor system. Upon issuance, instructions queued for the execution unit which occur after the first reservation instruction in the program order are flushed from the execution unit, in response to detecting any previously executed reservation instructions in the execution unit which occur after the first reservation instruction in the program order.

Abstract: A method and system for permitting nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of execution units on an opportunistic basis for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the results of the execution of each instruction to be stored within an intermediate storage buffer.

Abstract: A processor and method of interrupt handling in a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, in response to occurrence of an interrupt during emulation of a current guest instruction, an indication of a location in memory of the current guest instruction, an indication of a location in memory of a next guest instruction to be emulated, and an indication of a particular native instruction are stored. After an interrupt handler is executed, emulation is resumed by executing native instructions beginning with the particular native instruction. In response to execution of a native instruction of a first type before execution of a native instruction of a second type, the current guest instruction is fetched from memory.

Abstract: A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.

Abstract: A series of guest instructions including at least one guest branch instruction and other guest instructions are stored in memory. In addition, one or more semantic routines that are formed of native instructions and that may be utilized to emulate the series of guest instructions are stored in memory. For each other guest instruction in the series of guest instructions, an entry is stored in a multiple-entry queue in order of receipt of the other guest instructions. Each entry includes an indication of a location in memory of at least one semantic routine and a condition field indicating conditions that may be set or reset by the associated guest instruction. In response to the entries in the multiple-entry queue, the series of guest instructions are emulated in the processor by using the entries to access and execute selected ones of the one or more semantic routines.

Abstract: A method and system for input/output control in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously in response to one or more transfer requests. In response to a transfer request having a data address associated therewith, a particular target device is identified. The data address is then written into an address queue. Thereafter, one or more of the multiple sub-buses are utilized to transfer data to or from a single processor in response to a transfer request from a single processor. In response to a transfer request from multiple processors, one or more of the multiple sub-buses may be utilized separately to simultaneously transfer data to or from multiple processors.

Abstract: A method and system for arbitrating access to a component of a computer have been disclosed the method and system include an arbitration unit for granting access to the component; and a plurality of units for executing a plurality of transactions requiring access to the component. Each transaction of the plurality of transactions has an encoded priority. Each of the plurality of units further provide the arbitration unit with the encoded priority of each of the plurality of transactions. The arbitration unit grants a predetermined number of the plurality of units access to the component in response to the encoded priority of each of the predetermined plurality of transactions.

Abstract: A method and system for enhanced bus access in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a maximum-permitted number of sub-buses. If the number of sub-buses granted to a particular processor equals the number of pending transactions at that processor, all pending transactions are performed in parallel on separate sub-buses. If the number of sub-buses granted is less than the number of pending transactions, pending transactions are performed in a priority order.

Abstract: A method and system for enhanced bus arbitration in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a number of sub-buses. A maximum number of sub-buses is specified for each processor and the processors are prioritized. Each time a bus request is received from a processor, the number of requested sub-buses is granted, if that number is equal to or less than the specified maximum number of sub-buses for that processor. If the requested number of sub-buses is greater than the specified maximum number of sub-buses for that processor the requested number is granted if no other processor has issued a bus request.

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.

Abstract: A method and system for executing a context-altering instruction within a processor are disclosed. The processor has a superscalar architecture that includes multiple pipelines, buffers, registers, and execution units. The processor also includes a machine state register for identifying a context of the processor, and a shadow machine state register in conjunction with the machine state register. During operation, a first state of the machine state register is copied to the shadow machine state register. Instructions are executed in accordance with a context identified by the first state of the machine state register. The first state of the shadow machine state register is subsequently altered to a second state in response to decoding a context-altering instruction. The context-altering instruction and subsequent instructions are then executed in accordance with the second state of the shadow machine state register.