Patents by Inventor James Broc Stirton

James Broc Stirton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6549287
    Abstract: A method for polishing wafers includes polishing a process layer formed on a wafer, the process layer overlying a grating structure; illuminating at least a portion of the process layer and the grating structure; measuring light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile; comparing the measured reflection profile to a target reflection profile having an acceptable degree of planarity; and terminating the polishing of the process layer based on the comparison of the measured reflection profile and the target reflection profile. A metrology tool adapted to measure a wafer having a grating structure and a process layer formed over the grating structure after initiation of a polishing process includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the process layer overlying the grating structure.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: April 15, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin R. Lensing, James Broc Stirton
  • Patent number: 6529282
    Abstract: The present invention is generally directed to a method of controlling photolithography processes based upon scatterometric measurements of photoresist thickness, and system for accomplishing same. In one embodiment, the method comprises providing a library of optical characteristic traces, each of which corresponds to a grating structure comprised of a plurality of photoresist features having a known thickness, forming at least one grating structure in a layer of photoresist, the formed grating structure being comprised of a plurality of photoresist features having an unknown thickness, and illuminating the formed grating structure. The method further comprises measuring light reflected off of the formed grating structure to generate an optical characteristic trace for the formed grating structure, and determining the unknown thickness of the photoresist features by comparing the generated optical characteristic trace to at least one optical characteristic trace from the library.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: March 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Broc Stirton, Richard J. Markle
  • Patent number: 6524163
    Abstract: A method for polishing wafers includes providing a wafer having at least one alignment mark comprising a grating structure formed thereon; illuminating the grating structure of the alignment mark with a light source; measuring light reflected from the grating structure to generate a reflection profile; and determining at least one parameter of an operating recipe of a polishing tool adapted to polish a subsequent wafer to affect a polishing rate of the polishing tool in a region of the wafer where the alignment mark is disposed based on the reflection profile. A processing line includes a polishing tool, a metrology tool, and a process controller. The polishing tool is adapted to polish wafers in accordance with an operating recipe. The metrology tool is adapted to receive a wafer having at least one alignment mark comprising a grating structure formed thereon.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: February 25, 2003
    Assignee: Advanced Micro Devices Inc.
    Inventor: James Broc Stirton
  • Patent number: 6479200
    Abstract: A method of using scatterometric techniques to control stepper process is disclosed. In one illustrative embodiment, the method comprises providing a library of optical characteristic traces, each of which corresponds to a grating structure comprised of a plurality of photoresist features having a known profile, and forming at least one grating structure in a layer of photoresist, wherein the formed grating structure is comprised of a plurality of photoresist features having an unknown profile.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: November 12, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: James Broc Stirton
  • Patent number: 6458605
    Abstract: A method for controlling a photolithography process includes providing a wafer having a first grating structure and a second grating structure overlying the first grating structure; illuminating at least a portion of the first and second grating structures with a light source; measuring light reflected from the illuminated portion of the first and second grating structures to generate a reflection profile; determining an overlay error between the first and second grating structures based on the reflection profile; and determining at least one parameter of an operating recipe for a photolithography stepper based on the determined overlay error. A processing line includes a photolithography stepper, a first metrology tool, and a controller. The photolithography stepper is adapted to process wafers in accordance with an operating recipe. The first metrology tool is adapted to receive a wafer having a first grating structure and a second grating structure overlying the first grating structure.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: October 1, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: James Broc Stirton
  • Patent number: 6451700
    Abstract: A method for polishing wafers includes providing a wafer having a grating structure and a process layer formed over the grating structure; illuminating at least a portion of the process layer and the grating structure with a light source; measuring light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile; and determining planarity of the process layer based on the reflection profile. A metrology tool adapted to receive a wafer having a grating structure and a process layer formed over the grating structure includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the process layer overlying the grating structure. The detector is adapted to measure light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: September 17, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Broc Stirton, Kevin R. Lensing
  • Patent number: 6433871
    Abstract: A method of using scatterometry measurements to determine and control gate electrode profiles is disclosed. In one embodiment, the method comprises providing a library of optical characteristic traces, each of which correspond to a grating structure comprised of a plurality of gate electrode structures having a known profile, providing a substrate having at least one grating structure formed thereabove, the formed grating structure comprised of a plurality of gate electrode structures having an unknown profile, and illuminating the formed grating structure. The method further comprises measuring light reflected off of the grating structure to generate an optical characteristic trace for the formed grating structure and determining a profile of the gate electrode structures comprising the formed grating structure by correlating the generated optical characteristic trace to an optical characteristic trace from the library.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: August 13, 2002
    Assignee: Advanced Micron Devices, Inc.
    Inventors: Kevin R. Lensing, James Broc Stirton
  • Patent number: 6383888
    Abstract: A method for aligning wafers includes providing a wafer having at least a first and a second alignment mark formed thereon, each alignment mark comprising a grating structure; illuminating the grating structure of the first alignment mark with a light source; measuring light reflected from the grating Structure of the first alignment mark to generate a first reflection profile; illuminating the grating structure of the second alignment mark with the light source; measuring light reflected from the grating structure of the second alignment mark to generate a second reflection profile; and selecting one of the first and second alignment marks for aligning the wafer based on the first and second reflection profiles. A processing line includes a metrology tool and a process controller. The metrology tool is adapted to receive a wafer having at least a first and a second alignment mark formed thereon. Each alignment mark comprises a grating structure.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: May 7, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: James Broc Stirton