Abstract: A MESFET device is provided wherein the top Schottky gate is electrically isolated from the bottom gate. Methods as described for forming channels self aligned to Schottky top gates and complementary junction field effect transistors. A method is also described for adjusting or trimming the voltage to current characteristics of a MESFET by applying current pulses to the gate and through the channel to create conductive regions between the top and bottom gate. Dual segment gates or sources or drains may be provided to reduce the trimming current and appropriate steering circuitry also provided. This technique may be used to adjust individual MESFETs, as well as current followers, differential amplifiers and other circuits which would be designed to include MESFETs.

Abstract: Series resistance in the low impurity portion of a high breakdown PN junction of a three or four layer device is reduced by providing an increased impurity region at the junction of the same conductivity type as the low impurity portion and having an impurity profile such that the increased impurity region is depleted under reverse biasing before critical field is reached therein. The three layer device include insulated gate field effect transistors and bipolar devices and the four layer device is an SCR.

Abstract: A MESFET device is provided wherein the top Schottky gate is electrically isolated from the bottom gate. Methods as described for forming channels self aligned to Schottky top gates and complementary junction field effect transistors. A method is also described for adjusting or trimming the voltage to current characteristics of a MESFET by applying current pulses to the gate and through the channel to create conductive regions between the top and bottom gate. Dual segment gates or sources or drains may be provided to reduce the trimming current and appropriate steering circuity also provided. This technique may be used to adjust individual MESFETs, as well as current followers, differential amplifiers and other circuits which would be designed to include MESFETs.

Abstract: The threshold of a double diffused insulated gate field effect transistor is determined by selectively positioning the source in the decreasing impurity concentration region of the body to set the peak impurity concentration in the channel region for the desired threshold voltage without modification of the process.

Abstract: A MESFET including a Schottky top gate which extends across the channel region between the source and drain regions and beyond two opposed sides of the dielectric isolation onto the substrate in which the device is built. The portion of the top gate which extends across the channel is disconnected from the portion which extends across the substrate beyond the dielectric isolation. This may result from the removal of the gate material at the dielectric isolation or by the portion of the gate material which is on the dielectric isolation being vertically displaced and disconnected or discontinuous from the portion of the gate material which extends across the channel and that portion which extends across the substrate.

Abstract: In integrated circuits having device island separated laterally by support of polycrystalline regions and a dielectric layer, a shield layer is provided along the side walls at the dielectric layer having an impurity concentration sufficiently greater than the island's impurity concentration to eliminate support bias influence without seriously affecting the PN junction in the island. The shield impurity concentration is less than the region forming a PN junction with the island and preferably is below 1.times.10.sup.13 ions/cm.sup.2 and a peak impurity concentration less than 5.times.10.sup.16 ions/cm.sup.3.

Abstract: A JFET having top gate contact regions formed in either one or both of the source and drain regions at and contacting a substantial portion of the edge terminations of the top gate in the source and drain regions. The improved top gate contact region can be used in three and four terminal JFET's.

Abstract: The constraint on the channel thickness of a conductivity-modulated FET is reduced by forming the junction gate region of a pair of differentially doped regions, one inside the other. The first, larger region, which extends from the surface of the island region to a prescribed depth therein, has a lower impurity concentration and higher resistivity, approximating that of the island region in which it is formed. Disposed in a surface portion of this first, high resistivity, low impurity concentration region is a second, relatively shallow, region more heavily doped than the deeper high resistivity region. During the on-condition of the FET, the thickness of the channel is effectively region beneath the low impurity concentration gate region and the semiconductor material of the low impurity concentration gate region beneath the relatively shallow high impurity concentration low resistivity region formed therein.

Abstract: The present invention provides an improved lateral drift region for both bipolar and MOS devices where improved breakdown voltage and low ON resistance are desired. A top gate of the same conductivity type as the device region with which it is associated is provided along the surface of the substrate and overlying the lateral drift region. In an MOS device, the extremity of the lateral drift region curves up to the substrate surface beyond the extremity of the top gate to thereby provide contact between the JFET channel and the MOS channel.

Abstract: A high voltage bipolar and JFET have their gate and base connected and source and collector connected and the appropriate geometry for the bipolar to operate to its BV.sub.CBO limit. The collector and channel regions have the same depth and impurity concentration, the base and top gate regions have the same depth and impurity concentration and the emitter and source and drain regions have the same depth and impurity concentration.

Abstract: In integrated circuits having device islands separated laterally by support to polycrystalline regions and a dielectric layer, a shield layer is provided along the side walls at the dielectric layer having an impurity concentration sufficiently greater than the island's impurity concentration to eliminate support bias influence without seriously affecting the PN junction in the island. The shield impurity concentration is less than the region forming a PN junction with the island and preferably is below 1.times.10.sup.13 ions/cm.sup.2 and a peak impurity concentration less than 5.times.10.sup.16 ions/cm.sup.3.

Abstract: A high voltage bipolar and JFET have their gate and base connected and source and collector connected and the appropriate geometry for the bipolar to operate to its BV.sub.CBO limit. The collector and channel regions have the same depth and impurity concentration, the base and top gate regions have the same depth and impurity concentration and the emitter and source and drain regions have the same depth and impurity concentration.

Abstract: In accordance with the present invention, the inability of ohmic coupling to dielectrically provide isolated regions from the bottom surface of a support substrate is provided by a modified dielectric isolation structure in which bottom portions of selected dielectrically isolated island regions are contiguous with the material of the semiconductor bulk by which the dielectrically isolated island regions are supported by way of apertures through the dielectric isolation at these bottom portions. As a result, the supporting material of the bulk can be used to provide an ohmic coupling path from electrodes on the bottom surface of the wafer to the semiconductor material of selected island regions. For those dielectrically isolated regions, other than the selected regions, having a conductivity type opposite to that of the support substrate, complete dielectric isolation from the substrate is maintained, to prevent the existence of well-to-substrate PN junctions.

Abstract: A high voltage PN junction in which a surface layer of the more lightly doped side of the junction, adjacent to the heavily doped side of the junction, is doped more heavily than the rest of that region and with the same conductivity type. The increased doped region is formed so that an overlying field plate totally depletes it before critical field for avalanche is reached.

Abstract: An insulated gate field effect transistor having a minority carrier diode and a majority carrier diode formed in the drain region. The minority diode modulates the resistance of the drain while the majority diode decreases sensitivity to latch up. Alternatively, a minority diode only is formed in the drain and separated from the drain contact and source by the body and body contact. An improved SCR is formed using the two diode structures as the fourth layer. An improved diode can also be formed having both low turn-on and low series resistance.

Abstract: A plurality of logic gates having common data inputs are selected by activation and deactivation of switches connecting the logic gates to circuit power terminals. In one embodiment both power leads of the logic gate are connected by two power switches to two circuit power terminals. In a second embodiment, the first power lead of the logic gate is continuously connected to the first circuit power terminal and the second gate power lead is connected to the second circuit power terminal by a first power switch for a select and to the first circuit power terminal by a second power switch for a deselect. The second embodiment includes a buffer inverter on each logic gate output whose power leads are connected to the circuit power terminals as are the logic gates. Alternatively, the second switch could connect the input of the inverter to the first circuit power terminal for a deselect.

Abstract: An integrated circuit wherein the base and surface collector regions of the I.sup.2 L vertical transistor are formed by the same steps used to form the collector and base, respectively, of complementary bipolar transistors. Thus, a high voltage bipolar transistor of the same type as the vertical I.sup.2 L transistor may be formed using separate process steps, thereby optimizing the design of both devices.

Abstract: A bipolar transistor having a first and second selective collector region extending from a buried high impurity region to the surface of the substrate. The first selective region defines the plane breakdown voltage to be equivalent to the planar breakdown voltage of the base-collector junction and the selective regions and the buried layer form a low series resistance collector.

Abstract: A JFET having the top gate isolated from the bottom gate by an annulus source region and thin channel region and a top gate ohmic contact region isolated from the bottom gate by a deep isolation region. The isolation region and the top gate contact region are exterior the active channel region.

Abstract: A JFET having the top gate isolated from the bottom gate by an annulus source region and thin channel region and a top gate ohmic contact region isolated from the bottom gate by a deep isolation region. The isolation region and the top gate contact region are exterior the active channel region.