Abstract: The reduction in breakdown voltage of a device which contains adjoining regions of relatively high and low impurity concentrations within a dielectrically isolated island of an integrated circuit architecture is effectively countered by biasing the material surrounding the island, such as a support polysilicon substrate or the fill material of a isolated trench, at a prescribed bias voltage that is insufficient to cause the avalanche-generation of electron-hole pairs in the vicinity of the relatively high-to-low impurity concentration junction between the buried layer and the island. Where a plurality of islands are supported in and surrounded by a common substrate material of an overall integrated circuit architecture, the prescribed bias voltage may be set at a value that is no more positive than half the difference between the most positive and the most negative of the bias voltages that are applied to the integrated circuit.

Abstract: In a semiconductor island structure with passive side isolation, a method and structure for reducing corner breakdown where a device conductor crosses the edge of the island. The decrease in the field strength at the island edge between the conductor and the adjacent conducting region may be achieved by increasing the depth of the insulator beneath the conductor where it crosses the island edge without the necessity for increasing the thickness of the layer of insulation applied directly to the surface of the island by the use of a second or higher level interconnect, e.g., the conventional deposition of one or more additional layers of insulation over the device terminal to increase the spacing between the conductor and the surface of the island. In this way the process by which the device is constructed may remain unchanged.

Abstract: A contact region for a trench in a semiconductor device and a method for electrically contacting the conductive material in a trench that is too narrow for conventional electrical contacts may include a contact region in which the trench is divided into two or more trench sections, each section having the same narrow width as the undivided trench. The two or more trench sections are separated by one or more islands that are isolated from the semiconductor device. An aperture through the material above the contact region provides access for electrically contacting the conductive material in the trench sections.

Abstract: A punch-through diode includes a first and second gate forming first and second junctions respectively with and spaced from each other by a first region. The junctions may be PN junction or Schottky barrier junctions with the first region. The diode may be the top gate-channel-bottom gate junctions of an FET or the collector-base-emitter junctions of a bipolar transistor. In either case, the channel or the base is depleted and currents flow between the top and bottom gate or the emitter and collector respectively. The punch-through diode is used as a voltage reference element and can be structured for Kelvin connection.

Abstract: A punch-through diode includes a first and second gate forming first and second junctions respectively with and spaced from each other by a first region. The junctions may be PN junction or Schottky barrier junctions with the first region. The diode may be the top gate-channel-bottom gate junctions of an FET or the collector-base-emitter junctions of a bipolar transistor. In either case, the channel or the base is depleted and currents flow between the top and bottom gate or the emitter and collector respectively. The punch-through diode is used as a voltage reference element and can be structured for Kelvin connection.

Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

Abstract: A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base.

Abstract: The reduction in breakdown voltage of a device which contains adjoining regions of relatively high and low impurity concentrations within a dielectrically isolated island of an integrated circuit architecture is effectively countered by biasing the material surrounding the island, such as a support polysilicon substrate or the fill material of a isolated trench, at a prescribed bias voltage that is insufficient to cause the avalanche-generation of electron-hole pairs in the vicinity of the relatively high-to-low impurity concentration junction between the buried layer and the island. Where a plurality of islands are supported in and surrounded by a common substrate material of an overall integrated circuit architecture, the prescribed bias voltage may be set at a value that is no more positive than half the difference between the most positive and the most negative of the bias voltages that are applied to the integrated circuit.

Abstract: A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base.

Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

Abstract: In a semiconductor island structure with passive side isolation, a method and structure for reducing corner breakdown where a device conductor crosses the edge of the island. The decrease in the field strength at the island edge between the conductor and the adjacent conducting region may be achieved by increasing the depth of the insulator beneath the conductor where it crosses the island edge without the necessity for increasing the thickness of the layer of insulation applied directly to the surface of the island by the use of a second or higher level interconnect, e.g., the conventional deposition of one or more additional layers of insulation over the device terminal to increase the spacing between the conductor and the surface of the island. In this way the process by which the device is constructed may remain unchanged.

Abstract: A semiconductor device may include complementary NPN and PNP transistors and a JFET that is formed in the same steps as used to form the transistors. The bottom gate of the JFET and the back collector layer of the PNP transistor are doped and up-diffused in the same steps to cause the channel of the JFET and distance between the base and back collector layer of the PNP transistor to be the same. The JFET may have a low voltage capability (less than 5 volt pinch-off voltage) and the PNP transistor may have a breakdown voltage of at least 30 volts.

Abstract: A contact region for a trench in a semiconductor device and a method for electrically contacting the conductive material in a trench that is too narrow for conventional electrical contacts may include a contact region in which the trench is divided into two or more trench sections, each section having the same narrow width as the undivided trench. The two or more trench sections are separated by one or more islands that are isolated from the semiconductor device. An aperture through the material above the contact region provides access for electrically contacting the conductive material in the trench sections.

Abstract: Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS typography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the water and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.

Abstract: A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base.

Abstract: A dielectrically isolated island architecture in which the island is contoured inwardly to form one or more projections that penetrate a well separating two regions in the island to assure that the two regions will be electrically isolated without additional processing steps.

Abstract: A method of forming a capacitor in a bonded wafer using the same process steps used to form integrated circuit devices in the bonded wafer. The bonded wafer may comprise a device wafer and a handle wafer, each of which forms a capacitor plate, bonded together with a dielectric therebetween. The device wafer may be divided into one or more insulated islands for the formation of integrated circuit devices, and a dummy island external of the insulated islands. One or more capacitor plates may be formed from the dummy island in the device wafer. The device wafer may include buried layers and an isolation trench along an outer edge separating the semiconductor material of the die from the wafer. The wafer may also be formed by the ZMR and SIMOX processes. In addition, other circuit structures such as thin film resistors may be formed on or above the upper insulator.

Abstract: Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS typography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the wafer and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.

Abstract: A voltage divider including a plurality of series connected depletion mode field effect transistors having their gates and sources biased to operate in saturation mode for the operating range of the divider, Preferably, the gates and sources are connected together, A series resistor adjusts the value of the divider element. A parallel resistor defines the output resistance of the divider element. The voltage divider may be used as a biasing network for stacked transistors. A buffer may be provided between the voltage divider and the control terminal of the stacked transistors. The voltage divider may be used to bias follower stages and the input stages of an operational amplifier.