Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.

Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.

Abstract: A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event.

Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.

Abstract: An SRAM bit cell comprises a first inverter including a PMOS transistor and an NMOS transistor, and a second inverter including a PMOS transistor and an NMOS transistor. The first and second inverters are cross-coupled to each other. A plurality of pass transistors couple the inverters to bit lines. Approximately one-half of a supply voltage is provided to the bit lines during pre-charge operations.

Abstract: A memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN).

Abstract: Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations.

Abstract: Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations.

Abstract: A sensor circuit performs a method for sensing on-chip characteristics. The method includes generating a first voltage using a drive current through a first set of transistors that are operating in saturation mode and generating a second voltage using subthreshold leakage current from a second set of transistors that are in subthreshold mode. The method further includes comparing the second voltage to the first voltage to sense an on-chip characteristic. The sensed on-chip characteristic can be temperature and/or gate length variation.

Abstract: A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event.

Abstract: A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.

Abstract: An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal.

Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

Abstract: A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.

Abstract: Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. A contact extends into the first current electrode region and is electrically coupled to the first current electrode region.

Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.

Abstract: A memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN).

Abstract: An SRAM bit cell comprises a first inverter including a PMOS transistor and an NMOS transistor, and a second inverter including a PMOS transistor and an NMOS transistor. The first and second inverters are cross-coupled to each other. A plurality of pass transistors couple the inverters to bit lines. Approximately one-half of a supply voltage is provided to the bit lines during pre-charge operations.

Abstract: A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.

Abstract: A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.