Abstract: An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).

Abstract: A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.

Abstract: An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.

Abstract: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

Abstract: A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.

Abstract: A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.

Abstract: A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.

Abstract: A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.

Abstract: A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.

Abstract: A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.

Abstract: A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.

Abstract: An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells.

Abstract: A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.

Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

Abstract: A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device. The semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.

Abstract: A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.

Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

Abstract: A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

Abstract: An electronic device can include a static-random-access memory cell. The static-random-access memory cell can include a first transistor of a first type and a second transistor of a second type. The first transistor can have a first channel length extending along a first line, and the second transistor can have a second channel length extending along a second line. The first line and the second line can intersect at an angle having a value other than any integer multiple of 22.5°. In a particular embodiment, the first transistor can include a pull-up transistor, and the second transistor can include a pass gate or pull-down transistor. A process can be used to form semiconductor fins and conductive members, which include gate electrode portions, to achieve the electronic device including the first and second transistors.

Abstract: A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.