Patents by Inventor James G. Hermerding, II
James G. Hermerding, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230168732Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.Type: ApplicationFiled: August 4, 2022Publication date: June 1, 2023Applicant: Tahoe Research, Ltd.Inventors: Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II
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Patent number: 11500444Abstract: A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.Type: GrantFiled: May 8, 2020Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Leo Aqrabawi, Chia-hung S. Kuo, James G. Hermerding, II, Premanand Sakarda, Bijan Arbab, Kelan Silvester
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Patent number: 11435816Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.Type: GrantFiled: March 29, 2021Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II
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Patent number: 11301011Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.Type: GrantFiled: November 26, 2019Date of Patent: April 12, 2022Assignee: INTEL CORPORATIONInventors: Ketan R. Shah, Tawfik M. Rahal-Arabi, Eric DiStefano, James G. Hermerding, II
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Patent number: 11249537Abstract: When power is provided through a USB-C cable from a source device to a sink device, a sudden connection or disconnection of the cable between the two devices may cause a sudden power surge or power drop in at least one of those devices, leading to other problems. To avoid this sudden event from causing potential damage or disruption to one of the devices, in some embodiments a CC pin in the cable is used to announce the impending connection/disconnection, and the device may throttle back its power consumption before power is actually applied to or removed from the power pins.Type: GrantFiled: July 13, 2020Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Chee Lim Nge, Eugene Gorbatov, Zhongsheng Wang, James G. Hermerding, II, Basavaraj B. Astekar, Jenn Chuan Cheng, Chia-Hung Sophia Kuo, Ashwin Umapathy, Tin-Cheung Kung, Yifan Li, Alexander B. Uan-Zo-Li
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Patent number: 11209888Abstract: An embodiment of a semiconductor package apparatus may include technology to determine history information for a battery, predict a peak power capacity of the battery based on the history information, and set a peak power parameter based on the predicted peak power capacity.Type: GrantFiled: September 29, 2017Date of Patent: December 28, 2021Assignee: Intel CorporationInventors: James G. Hermerding, II, Alexander B. Uan-Zo-Li, Brian C. Fritz, Naoki Matsumura
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Publication number: 20210349522Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.Type: ApplicationFiled: March 29, 2021Publication date: November 11, 2021Inventors: Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II
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Publication number: 20210349519Abstract: A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.Type: ApplicationFiled: May 8, 2020Publication date: November 11, 2021Applicant: Intel CorporationInventors: Leo Aqrabawi, Chia-hung S. Kuo, James G. Hermerding II, Premanand Sakarda, Bijan Arbab, Kelan Silvester
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Patent number: 10990161Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.Type: GrantFiled: April 12, 2019Date of Patent: April 27, 2021Assignee: Intel CorporationInventors: Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II
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Publication number: 20200341530Abstract: When power is provided through a USB-C cable from a source device to a sink device, a sudden connection or disconnection of the cable between the two devices may cause a sudden power surge or power drop in at least one of those devices, leading to other problems. To avoid this sudden event from causing potential damage or disruption to one of the devices, in some embodiments a CC pin in the cable is used to announce the impending connection/disconnection, and the device may throttle back its power consumption before power is actually applied to or removed from the power pins.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Applicant: Intel CorporationInventors: Chee Lim Nge, Eugene Gorbatov, Zhongsheng Wang, James G. Hermerding, II, Basavaraj B. Astekar, Jenn Chuan Cheng, Chia-Hung Sophia Kuo, Ashwin Umapathy, Tin-Cheung Kung, Yifan Li, Alexander B. Uan-Zo-Li
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Patent number: 10761579Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.Type: GrantFiled: August 4, 2017Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Ankush Varma, Vasudevan Srinivasan, Eugene Gorbatov, Andrew D. Henroid, Barnes Cooper, David W. Browning, Guy M. Therien, Neil W. Songer, Krishnakanth V. Sistla, James G. Hermerding, II
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Patent number: 10739844Abstract: In one embodiment, a processor includes: a plurality of processing elements to perform operations; a power management agent (PMA) coupled to the plurality of processing elements to control power consumption of the plurality of processing elements; and a throttling circuit coupled to the PMA. The throttling circuit is to determine a throttling power level for the plurality of processing elements based at least in part on translation information communicated from the PMA. Other embodiments are described and claimed.Type: GrantFiled: May 2, 2018Date of Patent: August 11, 2020Assignee: Intel CorporationInventors: Chee Lim Nge, James G. Hermerding, II, Pronay Dutta, Joshua Resch
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Patent number: 10739842Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.Type: GrantFiled: April 1, 2017Date of Patent: August 11, 2020Assignee: Intel CorporationInventors: Eugene Gorbatov, Alexander B. Uan-Zo-Li, Muhammad Abozaed, Efraim Rotem, Tod F. Schiff, James G. Hermerding, II, Chee Lim Nge
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Patent number: 10712801Abstract: When power is provided through a USB-C cable from a source device to a sink device, a sudden connection or disconnection of the cable between the two devices may cause a sudden power surge or power drop in at least one of those devices, leading to other problems. To avoid this sudden event from causing potential damage or disruption to one of the devices, in some embodiments a CC pin in the cable is used to announce the impending connection/disconnection, and the device may throttle back its power consumption before power is actually applied to or removed from the power pins.Type: GrantFiled: June 30, 2017Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Chee Lim Nge, Eugene Gorbatov, Zhongsheng Wang, James G. Hermerding, II, Basavaraj B. Astekar, Jenn Chuan Cheng, Chia-Hung Sophia Kuo, Ashwin Umpathy, Tin-Cheung Kung, Yifan Li, Alexander B. Uan-Zo-Li
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Publication number: 20200218319Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.Type: ApplicationFiled: November 26, 2019Publication date: July 9, 2020Applicant: INTEL CORPORATIONInventors: Ketan R. Shah, Tawfik M. Rahal-Arabi, Eric DiStefano, James G. Hermerding, II
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Patent number: 10606338Abstract: Aspects of the embodiments are directed to systems, methods, and program products for rebalancing power in a multi-chip computing platform, which includes a core processor and a discrete peripheral processor. Embodiments include determining that the core processor and the discrete peripheral processor are in a limited usage state; altering a polling interval of the core processor and the discrete peripheral processor from a first polling time to a second polling time, the second polling time greater than the first polling time; and polling the core processor and the discrete peripheral processor after an expiration of the second polling time. Embodiments also include using thermal and/or energy consumption data to dynamically adjust polling times to permit the core processor and the discrete peripheral processor to remain in an idle or low power state for as long as possible.Type: GrantFiled: December 29, 2017Date of Patent: March 31, 2020Assignee: Intel CorporationInventors: Sudheer Nair, James G. Hermerding, II, Avinash Ananthakrishnan
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Patent number: 10488899Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.Type: GrantFiled: July 12, 2017Date of Patent: November 26, 2019Assignee: Intel CorporationInventors: Ketan R. Shah, Tawfik M. Rahal-Arabi, Eric Distefano, James G. Hermerding, II
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Patent number: 10468730Abstract: Various embodiments may be generally directed to techniques for using an observed battery stress history to manage operation of a computing system component in a high power performance mode when powered by a battery. Various embodiments include techniques for tracking stresses to a battery. Various embodiments include techniques for comparing the battery stress history to a degradation baseline for the battery. Various embodiments include techniques for developing a degradation baseline for a battery including, for example, a degradation baseline based on expected stress to a battery and/or a degradation baseline based on a battery reliability model. Various embodiments include techniques for determining a battery stress surplus or deficit. Various embodiments include techniques for managing operation of a performance enhancing mode or high power performance mode of a computing system component based on the determined battery stress surplus or deficit.Type: GrantFiled: September 26, 2015Date of Patent: November 5, 2019Assignee: INTEL CORPORATIONInventors: Jorge P. Rodriguez, Alexander B. Uan-Zo-Li, Naoki Matsumura, Andrew Keates, James G. Hermerding, II
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Patent number: 10423202Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.Type: GrantFiled: April 7, 2016Date of Patent: September 24, 2019Assignee: Intel CorporationInventors: Efraim Rotem, Tod F. Schiff, Doron Rajwan, Jeffrey M. Jull, James G. Hermerding, II, Nir Rosenzweig, Maytal Toledano, Alexander B. Uan-Zo-Li
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Publication number: 20190235618Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.Type: ApplicationFiled: April 12, 2019Publication date: August 1, 2019Inventors: Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II