Abstract: Aspects of the embodiments are directed to systems, methods, and program products for rebalancing power in a multi-chip computing platform, which includes a core processor and a discrete peripheral processor. Embodiments include determining that the core processor and the discrete peripheral processor are in a limited usage state; altering a polling interval of the core processor and the discrete peripheral processor from a first polling time to a second polling time, the second polling time greater than the first polling time; and polling the core processor and the discrete peripheral processor after an expiration of the second polling time. Embodiments also include using thermal and/or energy consumption data to dynamically adjust polling times to permit the core processor and the discrete peripheral processor to remain in an idle or low power state for as long as possible.

Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine history information for a battery, predict a peak power capacity of the battery based on the history information, and set a peak power parameter based on the predicted peak power capacity.

Abstract: In one embodiment, a processor includes: a plurality of processing elements to perform operations; a power management agent (PMA) coupled to the plurality of processing elements to control power consumption of the plurality of processing elements; and a throttling circuit coupled to the PMA. The throttling circuit is to determine a throttling power level for the plurality of processing elements based at least in part on translation information communicated from the PMA. Other embodiments are described and claimed.

Abstract: When power is provided through a USB-C cable from a source device to a sink device, a sudden connection or disconnection of the cable between the two devices may cause a sudden power surge or power drop in at least one of those devices, leading to other problems. To avoid this sudden event from causing potential damage or disruption to one of the devices, in some embodiments a CC pin in the cable is used to announce the impending connection/disconnection, and the device may throttle back its power consumption before power is actually applied to or removed from the power pins.

Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.

Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.

Abstract: A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

Abstract: An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.

Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.

Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.

Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.

Abstract: Various embodiments may be generally directed to techniques for using an observed battery stress history to manage operation of a computing system component in a high power performance mode when powered by a battery. Various embodiments include techniques for tracking stresses to a battery. Various embodiments include techniques for comparing the battery stress history to a degradation baseline for the battery. Various embodiments include techniques for developing a degradation baseline for a battery including, for example, a degradation baseline based on expected stress to a battery and/or a degradation baseline based on a battery reliability model. Various embodiments include techniques for determining a battery stress surplus or deficit. Various embodiments include techniques for managing operation of a performance enhancing mode or high power performance mode of a computing system component based on the determined battery stress surplus or deficit.

Abstract: An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.

Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.

Abstract: An electronic device comprising: a power monitor to receive system power to be delivered to a processor and to one or more components of a system, the power monitor to provide information corresponding to the system power, and a processor to change a performance of the processor based at least in part on the information corresponding to the system power.