Abstract: A method of partitioning a data cache comprising a plurality of sets, the plurality of sets comprising a plurality of ways, is provided. Responsive to a stack data request, the method stores a cache line associated with the stack data in one of a plurality of designated ways of the data cache, wherein the plurality of designated ways is configured to store all requested stack data.

Abstract: A method of storing stack data in a cache hierarchy is provided. The cache hierarchy comprises a data cache and a stack filter cache. Responsive to a request to access a stack data block, the method stores the stack data block in the stack filter cache, wherein the stack filter cache is configured to store any requested stack data block.

Abstract: The described embodiments include a core that uses predictions for store-to-load forwarding. In the described embodiments, the core comprises a load-store unit, a store buffer, and a prediction mechanism. During operation, the prediction mechanism generates a prediction that a load will be satisfied using data forwarded from the store buffer because the load loads data from a memory location in a stack. Based on the prediction, the load-store unit first sends a request for the data to the store buffer in an attempt to satisfy the load using data forwarded from the store buffer. If data is returned from the store buffer, the load is satisfied using the data. However, if the attempt to satisfy the load using data forwarded from the store buffer is unsuccessful, the load-store unit then separately sends a request for the data to a cache to satisfy the load.

Abstract: A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.

Abstract: The described embodiments include a computing device that handles memory requests. In some embodiments, when a memory request is to be sent to a cache in the computing device or to be bypassed to a next lower level of a memory hierarchy in the computing device based on expected memory request resolution times, a bypass mechanism is configured to send the memory request to the cache or bypass the memory request to the next lower level of the memory hierarchy.

Abstract: A device receives an indication that a memory bank is to be powered down, and determines, based on receiving the indication, shutdown scores corresponding to powered up memory banks. Each shutdown score is based on a shutdown metric associated with powering down a powered up memory bank. The device may power down a selected memory bank based on the shutdown scores.

Abstract: A device receives an indication that a memory bank is to be powered up, and determines, based on receiving the indication, power scores corresponding to powered down memory banks. Each power score corresponds to a power metric associated with powering up a powered down memory bank. The device powers up a selected memory bank based on the plurality of power scores.

Abstract: The present disclosure relates to a method and apparatus for dynamically controlling power consumption by at least one processor. A power management method includes monitoring, by power control logic of the at least one processor, performance data associated with each of a plurality of executions of a repetitive workload by the at least one processor. The method includes adjusting, by the power control logic following an execution of the repetitive workload, an operating frequency of at least one of a compute unit and a memory controller upon a determination that the at least one processor is at least one of compute-bound and memory-bound based on monitored performance data associated with the execution of the repetitive workload.

Abstract: A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence.

Abstract: A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.

Abstract: A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a helper processor that executes instructions to perform tasks in response to a task request from the processor devices or otherwise on behalf of the other processor devices. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the processor devices. The memory interface operates to perform memory accesses for the processor devices and for the helper processor. By virtue of the helper processor's tight integration with the stacked memory layers, the helper processor may perform certain memory-intensive operations more efficiently than could be performed by the external processor devices.

Abstract: An apparatus and method to enable a fast cache shutdown is disclosed. In one embodiment, a cache subsystem includes a cache memory and a cache controller coupled to the cache memory. The cache controller is configured to, upon restoring power to the cache subsystem, inhibit writing of modified data exclusively into the cache memory.

Abstract: According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data.

Abstract: A method and apparatus for obtaining overhead information by a mobile is provided herein. During operation, the mobile will be communicating with a first system on an active data channel. The mobile node will be able to measure pilot PN phase and amplitude for a second system that is a potential candidate to handoff and will have that information available. The data channel of the active service is used to query a proxy server that provides overhead information for the second base station. More particularly, when PN phase and amplitude information is provided to the proxy server, the proxy server will identify the base station and provide the overhead information needed to associate with the second base station.

Abstract: Embodiments of the present invention sets forth a method and system for reducing memory bandwidth requirements for an anti-aliasing operation. The first virtual coverage information for a pixel involved in an anti-aliasing operation is maintained in memory. If a certain operating condition of the anti-aliasing operation deterministically implies the second virtual coverage information for this pixel, the second virtual coverage information, as opposed to the first virtual coverage information, is used in the anti-aliasing operation. In such situations, since the virtual coverage information is implied, it does not have to be accessed from memory, thereby improving overall system performance.

Abstract: A base station (103) assigns a set of mobile stations (101) to a group wherein the group will share a set of radio resources. A shared control channel information element (501) is sent to the group of mobile stations (101) and provides a bitmap having fields for a control header (502), utilized resources (510), and first HARQ transmission assignments (530). HARQ subgroups may be defined to associate subgroups of mobile stations with specific HARQ transmission opportunities on the super-frame. The mobile stations (101) are assigned resources in a persistent manner in each long frame of a super-frame for which a first HARQ transmission opportunity is defined.

Abstract: A base station (103) assigns a set of mobile stations (101) to a group wherein the group will share a set of radio resources (770). A shared control channel information element (501) is sent to the group of mobile stations (101) and provides a bitmap having fields for group ordering (511), resource allocations (530), continuation resources (540) for HARQ, and an ordering pattern (513). If a mobile station requires retransmission it will access the resources indicated by the continuation resources field (54) in order to receive data. The HARQ blocks may be assigned to a mobile station based upon an index (601) which may correspond to the mobile station vocoder rate. Further, HARQ subgroups may be defined to associate subgroups of mobile stations with specific HARQ transmission opportunities on the super-frame and allocated by a rotating bitmap.

Abstract: A base station (103) assigns a set of mobile stations (101) to a group wherein the group will share a set of radio resources (710). A shared control channel information element (501) is sent to the group of mobile stations (101) and provides a bitmap having fields for group ordering (511), resource allocations (530), failure handling resources (540), and an ordering pattern (513). If a mobile station fails to decode the shared control channel information element (501) it will access the failure handling resources in order to receive data. The failure handling channel may be persistent in some embodiments, or may be released after the mobile station is once again able to decode the shared control channel information element (501) and thereby share in the shared resource pool allocated to its mobile station group.

Abstract: A wireless communication infrastructure entity assigns a plurality of schedulable wireless communication entities to a group wherein each entity is assigned a location within the group. The infrastructure entity indicates which of the plurality of schedulable wireless communication entities assigned to the group have been assigned a wireless resource, for example using a terminal assignments field (910) and indicates special transmission information using a special transmissions field (905). The special transmissions field (905) is used to indicate which of the schedulable wireless communication entities are receiving a special transmission.

Abstract: During operation a wireless terminal will receive instructions assigning it to a group of wireless terminals sharing a common set of resources. The terminal will also receive an overflow allocation policy indicating resources that are to be utilized if there are more assigned resources that group resources.