Patents by Inventor James R. Elliott
James R. Elliott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100032796Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.Type: ApplicationFiled: August 7, 2008Publication date: February 11, 2010Inventors: Brennan J. Brown, James R. Elliott, Alvin A. Joseph, Edward J. Nowak
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Publication number: 20100035403Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.Type: ApplicationFiled: August 7, 2008Publication date: February 11, 2010Inventors: Brennan J. Brown, James R. Elliott, Alvin J. Joseph, Edward J. Nowak
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Publication number: 20100027746Abstract: A new X-ray diffraction (XRD) method is provided to acquire XY mapping of the distribution of single crystals, poly-crystals, and twin defects across an entire wafer of rhombohedral super-hetero-epitaxial semiconductor material. In one embodiment, the method is performed with a point or line X-ray source with an X-ray incidence angle approximating a normal angle close to 90°, and in which the beam mask is preferably replaced with a crossed slit. While the wafer moves in the X and Y direction, a narrowly defined X-ray source illuminates the sample and the diffracted X-ray beam is monitored by the detector at a predefined angle. Preferably, the untilted, asymmetric scans are of {440} peaks, for twin defect characterization.Type: ApplicationFiled: October 20, 2008Publication date: February 4, 2010Applicant: U.S.A. as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon PARK, Sang Hyouk Choi, Glen C. King, James R. Elliott, Albert L. Dimarcantonio
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Publication number: 20090231677Abstract: An optical assembly includes a zone plate and electro-optic material disposed on one side of the zone plate. The electro-optic material's index of refraction is controlled to adjust the optical properties of the optical assembly.Type: ApplicationFiled: March 13, 2008Publication date: September 17, 2009Applicant: USA as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott
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Publication number: 20090220047Abstract: “Super-hetero-epitaxial” combinations comprise epitaxial growth of one material on a different material with different crystal structure. Compatible crystal structures may be identified using a “Tri-Unity” system. New bandgap engineering diagrams are provided for each class of combination, based on determination of hybrid lattice constants for the constituent materials in accordance with lattice-matching equations. Using known bandgap figures for previously tested materials, new materials with lattice constants that match desired substrates and have the desired bandgap properties may be formulated by reference to the diagrams and lattice matching equations. In one embodiment, this analysis makes it possible to formulate new super-hetero-epitaxial semiconductor systems, such as systems based on group IV alloys on c-plane LaF3; group IV alloys on c-plane langasite; Group III-V alloys on c-plane langasite; and group II-VI alloys on c-plane sapphire.Type: ApplicationFiled: October 20, 2008Publication date: September 3, 2009Applicants: Space AdministrationInventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott
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Publication number: 20090206368Abstract: Growth conditions are developed, based on a temperature-dependent alignment model, to enable formation of cubic group IV, group II-V and group II-VI crystals in the [111] orientation on the basal (0001) plane of trigonal crystal substrates, controlled such that the volume percentage of primary twin crystal is reduced from about 40% to about 0.3%, compared to the majority single crystal. The control of stacking faults in this and other embodiments can yield single crystalline semiconductors based on these materials that are substantially without defects, or improved thermoelectric materials with twinned crystals for phonon scattering while maintaining electrical integrity. These methods can selectively yield a cubic-on-trigonal epitaxial semiconductor material in which the cubic layer is substantially either directly aligned, or 60 degrees-rotated from, the underlying trigonal material.Type: ApplicationFiled: October 20, 2008Publication date: August 20, 2009Applicant: U.S.A as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang Hyouk Choi, Glen C. King, James R. Elliott
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Publication number: 20090203196Abstract: Metal and semiconductor nanoshells, particularly transition metal nanoshells, are fabricated using dendrimer molecules. Metallic colloids, metallic ions or semiconductors are attached to amine groups on the dendrimer surface in stabilized solution for the surface seeding method and the surface seedless method, respectively. Subsequently, the process is repeated with additional metallic ions or semiconductor, a stabilizer, and NaBH4 to increase the wall thickness of the metallic or semiconductor lining on the dendrimer surface. Metallic or semiconductor ions are automatically reduced on the metallic or semiconductor nanoparticles causing the formation of hollow metallic or semiconductor nanoparticles. The void size of the formed hollow nanoparticles depends on the dendrimer generation. The thickness of the metallic or semiconductor thin film around the dendrimer depends on the repetition times and the size of initial metallic or semiconductor seeds.Type: ApplicationFiled: December 4, 2008Publication date: August 13, 2009Applicants: National Institute of Aerospace Associates, USA as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Jae-Woo KIM, Sang H. CHOI, SR., Peter T. LILLEHEI, Sang-Hyon CHU, Yeonjoon PARK, Glen C. KING, James R. ELLIOTT, JR.
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Publication number: 20090185942Abstract: A novel method to prepare an advanced thermoelectric material has hierarchical structures embedded with nanometer-sized voids which are key to enhancement of the thermoelectric performance. Solution-based thin film deposition technique enables preparation of stable film of thermoelectric material and void generator (voigen). A subsequent thermal process creates hierarchical nanovoid structure inside the thermoelectric material. Potential application areas of this advanced thermoelectric material with nanovoid structure are commercial applications (electronics cooling), medical and scientific applications (biological analysis device, medical imaging systems), telecommunications, and defense and military applications (night vision equipments).Type: ApplicationFiled: December 4, 2008Publication date: July 23, 2009Applicants: National Institute of Aerospace Associates, Space AdminstrationInventors: Sang Hyouk Choi, SR., Yeonjoon Park, Sang-Hyon Chu, James R. Elliott, Glen C. King, Jae-Woo Kim, Peter T. Lillehei, Diane M. Stoakley
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Patent number: 7558371Abstract: A method provides X-ray diffraction data suitable for integral detection of a twin defect in a strained or lattice-matched epitaxial material made from components having crystal structures having symmetry belonging to different space groups. The material is mounted in an X-ray diffraction (XRD) system. In one embodiment, the XRD system's goniometer angle ? is set equal to (?B??) where ?B is a Bragg angle for a designated crystal plane of the alloy that is disposed at a non-perpendicular orientation with respect to the {111) crystal plane, and ? is the angle between the designated crystal plane and a {111} crystal plane of one of the epitaxial components. The XRD system's detector angle is set equal to (?B+?). The material can be rotated through an angle of azimuthal rotation ? about the axis aligned with the material. Using the detector, the intensity of the X-ray diffraction is recorded at least at the angle at which the twin defect occurs.Type: GrantFiled: October 20, 2008Date of Patent: July 7, 2009Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang Hyouk Choi, Glen C. King, James R. Elliott
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Publication number: 20090165837Abstract: New thermoelectric materials comprise highly [111]-oriented twinned group IV alloys on the basal plane of trigonal substrates, which exhibit a high thermoelectric figure of merit and good material performance, and devices made with these materials.Type: ApplicationFiled: October 20, 2008Publication date: July 2, 2009Applicants: Space AdministrationInventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott, Noel A. Talcott
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Publication number: 20090103680Abstract: A method provides X-ray diffraction data suitable for integral detection of a twin defect in a strained or lattice-matched epitaxial material made from components having crystal structures having symmetry belonging to different space groups. The material is mounted in an X-ray diffraction (XRD) system. In one embodiment, the XRD system's goniometer angle ? is set equal to (?B??) where ?B is a Bragg angle for a designated crystal plane of the alloy that is disposed at a non-perpendicular orientation with respect to the {111) crystal plane, and ? is the angle between the designated crystal plane and a {111} crystal plane of one of the epitaxial components. The XRD system's detector angle is set equal to (?B+?). The material can be rotated through an angle of azimuthal rotation ? about the axis aligned with the material. Using the detector, the intensity of the X-ray diffraction is recorded at least at the angle at which the twin defect occurs.Type: ApplicationFiled: October 20, 2008Publication date: April 23, 2009Applicant: U.S.A as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang Hyouk Choi, Glen C. King, James R. Elliott
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Patent number: 7514726Abstract: A lattice matched silicon germanium (SiGe) semiconductive alloy is formed when a {111} crystal plane of a cubic diamond structure SiGe is grown on the {0001} C-plane of a single crystalline Al2O3 substrate such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,?1,0> orientation of the {0001} C-plane. A lattice match between the substrate and the SiGe is achieved by using a SiGe composition that is 0.7223 atomic percent silicon and 0.2777 atomic percent germanium. A layer of Si1-xGex is formed on the cubic diamond structure SiGe. The value of X (i) defines an atomic percent of germanium satisfying 0.2277<X<1.0, (ii) is approximately 0.2777 where the layer of Si1-xGex interfaces with the cubic diamond structure SiGe, and (iii) increases linearly with the thickness of the layer of Si1-xGex.Type: GrantFiled: March 21, 2006Date of Patent: April 7, 2009Assignee: The United States of America as represented by the Aministrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott, Jr., Diane M. Stoakley
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Patent number: 7510802Abstract: A thin-film electrode for a bio-nanobattery is produced by consecutively depositing arrays of a ferritin protein on a substrate, employing a spin self-assembly procedure. By this procedure, a first ferritin layer is first formed on the substrate, followed by building a second, oppositely-charged ferritin layer on the top of the first ferritin layer to form a bilayer structure. Oppositely-charged ferritin layers are subsequently deposited on top of each other until a desired number of bilayer structures is produced. An ordered, uniform, stable and robust, thin-film electrode material of enhanced packing density is presented, which provides optimal charge density for the bio-nanobattery.Type: GrantFiled: March 9, 2006Date of Patent: March 31, 2009Assignees: National Institute of Aerospace Associates, The United States of America as represented by the Administration of NASAInventors: Sang-Hyon Chu, Sang H. Choi, Jae-Woo Kim, Peter T. Lillehei, Yeonjoon Park, Glen C. King, James R. Elliott, Jr.
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Publication number: 20090072078Abstract: A new High Altitude Airship (HAA) capable of various extended applications and mission scenarios utilizing inventive onboard energy harvesting and power distribution systems. The power technology comprises an advanced thermoelectric (ATE) thermal energy conversion system. The high efficiency of multiple stages of ATE materials in a tandem mode, each suited for best performance within a particular temperature range, permits the ATE system to generate a high quantity of harvested energy for the extended mission scenarios. When the figure of merit 5 is considered, the cascaded efficiency of the three-stage ATE system approaches an efficiency greater than 60 percent.Type: ApplicationFiled: July 31, 2007Publication date: March 19, 2009Applicants: Space AdministrationInventors: Sang H. Choi, James R. Elliott, JR., Glen C. King, Yeonjoon Park, Jae-Woo Kim, Sang-Hyon Chu
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Patent number: 7446007Abstract: A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.Type: GrantFiled: November 17, 2006Date of Patent: November 4, 2008Assignee: International Business Machines CorporationInventors: James W. Adkisson, Marc W. Cantell, James R. Elliott, James V. Hart, III, Dale W. Martin
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Patent number: 7379231Abstract: A light control device is formed by ferroelectric material and N electrodes positioned adjacent thereto to define an N-sided regular polygonal region or circular region therebetween where N is a multiple of four.Type: GrantFiled: September 7, 2006Date of Patent: May 27, 2008Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang H. Choi, Glen C. King, Jae-Woo Kim, James R. Elliott, Jr.
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Publication number: 20080116493Abstract: A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.Type: ApplicationFiled: November 17, 2006Publication date: May 22, 2008Inventors: James W. Adkisson, Marc W. Cantell, James R. Elliott, James V. Hart, Dale W. Martin
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Publication number: 20080074723Abstract: A light control device is formed by ferroelectric material and N electrodes positioned adjacent thereto to define an N-sided regular polygonal region or circular region therebetween where N is a multiple of four.Type: ApplicationFiled: September 7, 2006Publication date: March 27, 2008Applicant: U.S.A. as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang H. Choi, Glen C. King, Jae-Woo Kim, James R. Elliott
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Patent number: 7342290Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.Type: GrantFiled: November 4, 2004Date of Patent: March 11, 2008Assignee: International Business Machines CorporationInventors: Jay S. Burnham, James R. Elliott, Kenneth R. Gault, Mousa H. Ishaq, Steven M. Shank, Mary A. St. Lawrence
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Publication number: 20080014621Abstract: Metal nanoshells are fabricated by admixing an aqueous solution of metal ions with an aqueous solution of apoferritin protein molecules, followed by admixing an aqueous solution containing an excess of an oxidizing agent for the metal ions. The apoferritin molecules serve as bio-templates for the formation of metal nanoshells, which form on and are bonded to the inside walls of the hollow cores of the individual apoferritin molecules. Control of the number of metal atoms which enter the hollow core of each individual apoferritin molecule provides a hollow metal nonparticle, or nanoshell, instead of a solid spherical metal nanoparticle.Type: ApplicationFiled: July 12, 2007Publication date: January 17, 2008Applicant: National Institute of Aerospace AssociatesInventors: Jae-Woo Kim, Sang H. Choi, Peter T. Lillehei, Sang-Hyon Chu, Yeonjoon Park, Glen C. King, James R. Elliott