Patents by Inventor James S. Dunn
James S. Dunn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120275080Abstract: A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.Type: ApplicationFiled: April 28, 2011Publication date: November 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JAMES S. DUNN, Zhong-Xiang He, Anthony K. Stamper
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Publication number: 20120261719Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.Type: ApplicationFiled: June 21, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James S. DUNN, Alvin J. JOSEPH, Anthony K. STAMPER
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Patent number: 8237191Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.Type: GrantFiled: August 11, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: James S. Dunn, Alvin J. Joseph, Anthony K. Stamper
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Publication number: 20120187536Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.Type: ApplicationFiled: March 22, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James S. DUNN, Zhong - Xiang HE, Anthony K. STAMPER
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Publication number: 20120190190Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James S. DUNN, Alvin J. JOSEPH, Anthony K. STAMPER
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Patent number: 8191217Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.Type: GrantFiled: August 5, 2009Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
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Publication number: 20120038024Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.Type: ApplicationFiled: August 10, 2010Publication date: February 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan B. BOTULA, Dinh DANG, James S. DUNN, Alvin J. JOSEPH, Peter J. LINDGREN
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Patent number: 7932155Abstract: A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.Type: GrantFiled: June 8, 2007Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: James S. Dunn, David L. Harame, Jeffrey B. Johnson, Alvin J. Joseph
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Patent number: 7898061Abstract: A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.Type: GrantFiled: April 27, 2007Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: James S. Dunn, David L. Harame, Jeffrey B. Johnson, Alvin J. Joseph
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Publication number: 20110037096Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.Type: ApplicationFiled: August 11, 2009Publication date: February 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James S. DUNN, Alvin J. JOSEPH, Anthony K. STAMPER
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Publication number: 20110032659Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.Type: ApplicationFiled: August 5, 2009Publication date: February 10, 2011Applicant: International Business Machines CorporationInventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
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Publication number: 20110032660Abstract: A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.Type: ApplicationFiled: August 5, 2009Publication date: February 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
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Patent number: 7814454Abstract: A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.Type: GrantFiled: June 28, 2007Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Anthony I. Chou, James S. Dunn, Brian M. Dufrene, Christopher H. Lumbra, Shreesh Narasimha, Christopher S. Putnam, BethAnn Rainey, Christopher M. Schnabel
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Patent number: 7776704Abstract: The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.Type: GrantFiled: July 30, 2007Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: James S. Dunn, Alvin J. Joseph, Qizhi Liu
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Publication number: 20090007051Abstract: A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.Type: ApplicationFiled: June 28, 2007Publication date: January 1, 2009Inventors: Anthony I. Chou, James S. Dunn, Brian M. Dufrene, Christopher H. Lumbra, Shreesh Narasimha, Christopher S. Putnam, BethAnn Rainey, Christopher M. Schnabel
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Patent number: 7303968Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.Type: GrantFiled: December 13, 2005Date of Patent: December 4, 2007Assignee: International Business Machines CorporationInventors: James S. Dunn, Louis D. Lanzerotti, Steven H. Voldman
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Patent number: 7265018Abstract: The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.Type: GrantFiled: September 21, 2004Date of Patent: September 4, 2007Assignee: International Business Machines CorporationInventors: James S. Dunn, Alvin J. Joseph, Qizhi Liu
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Patent number: 7262484Abstract: A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.Type: GrantFiled: May 9, 2005Date of Patent: August 28, 2007Assignee: International Business Machines CorporationInventors: James S. Dunn, David L. Harame, Jeffrey B. Johnson, Alvin J. Joseph
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Patent number: 7253096Abstract: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.Type: GrantFiled: November 30, 2005Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Marwan H. Khater, James S. Dunn, David L. Harame, Alvin J. Joseph, Qizhi Liu, Francois Pagette, Stephen A. St. Onge, Andreas D. Stricker
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Patent number: 7135375Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.Type: GrantFiled: February 8, 2005Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, James S. Dunn, Michael D. Gordon, Mohamed Y. Hammad, Jeffrey B. Johnson, David C. Sheridan