Abstract: The preferred embodiment of the present invention overcomes the disadvantages of the prior art by using hybrid resist to define a sidewall spacer region and form a new type of sidewall spacer. The preferred method allows for more controlled doping at the gate-source and gate-drain junctions by defining sidewall spacer troughs using hybrid resist. Implants can then be made through the troughs to precisely control the doping at the gate junctions. Additionally, sidewall spacers can then be formed in the sidewall spacer troughs. The dimensions of the sidewall spacers is determined by the hybrid resist and can thus be made smaller than traditional resist processes. Additionally, forming the sidewall spacers using hybrid resist allows for their width to be determined independent of the depth of the gate material.

Abstract: An isolation method in which an isolation ring is formed to isolate a semiconductor device from other semiconductor devices on a common substrate. The method is suitable for isolating bipolar devices from CMOS or other devices formed on the same substrate and for preventing base current from being injected into the substrate. The method starts with a substrate having a buried sub-collector and a first isolation region that surrounds the portion of the surface to contain the semiconductor device. The first isolation region extends only part of the distance from the surface towards the buried sub-collector. Layers of polysilicon and dual-tone resist are applied, and a first mask is used with an opaque area aligned over the portion of the surface to contain the semiconductor device. The edge of the opaque region terminates above the first isolation region. After exposure, the properties of the dual-tone resist allow a narrow sub-minimum width trench to be removed from the resist to define an isolation ring.

Abstract: The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

Abstract: The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

Abstract: The invention is a method of fabricating a self-aligned, sub-minimum guard ring for a Schottky diode device wherein the sub-minimum guard ring is positioned at the inside edges of adjacent isolation structures and is self-aligned to the intrinsic base implanted regions. In this particular invention, illustrating the guard ring fabrication technique, an improved Schottky diode is fabricated at minimum groundrules which utilizes a frequency-doubling resist and an appropriate mask to provide the implant mask for a p- or n-type guard ring. This shallow implant near the surface prepares a guard ring that minimizes the electric field at the interface where the deposited metal or silicide joins the STI structure. Additional ion implants with energies greater than and less than the guard ring implantation energy may be deposited to tailor the substrate surface and reduce the parasitic capacitance of the diode.

Abstract: The preferred embodiment of the present invention overcomes the disadvantages of the prior art by using hybrid resist to define a sidewall spacer region and form a new type of sidewall spacer. The preferred method allows for more controlled doping at the gate-source and gate-drain junctions by defining sidewall spacer troughs using hybrid resist. Implants can then be made through the troughs to precisely control the doping at the gate junctions. Additionally, sidewall spacers can then be formed in the sidewall spacer troughs. The dimensions of the sidewall spacers is determined by the hybrid resist and can thus be made smaller than traditional resist processes. Additionally, forming the sidewall spacers using hybrid resist allows for their width to be determined independent of the depth of the gate material.

Abstract: The preferred embodiment of the present invention overcomes the disadvantages of the prior art by using hybrid resist to define a sidewall spacer region and form a new type of sidewall spacer. The preferred method allows for more controlled doping at the gate-source and gate-drain junctions by defining sidewall spacer troughs using hybrid resist. Implants can then be made through the troughs to precisely control the doping at the gate junctions. Additionally, sidewall spacers can then be formed in the sidewall spacer troughs. The dimensions of the sidewall spacers is determined by the hybrid resist and can thus be made smaller than traditional resist processes. Additionally, forming the sidewall spacers using hybrid resist allows for their width to be determined independent of the depth of the gate material.

Abstract: An isolation method in which an isolation ring is formed to isolate a semiconductor device from other semiconductor devices on a common substrate. The method is suitable for isolating bipolar devices from CMOS or other devices formed on the same substrate and for preventing base current from being injected into the substrate. The method starts with a substrate having a buried sub-collector and a first isolation region that surrounds the portion of the surface to contain the semiconductor device. The first isolation region extends only part of the distance from the surface towards the buried sub-collector. Layers of polysilicon and dual-tone resist are applied, and a first mask is used with an opaque area aligned over the portion of the surface to contain the semiconductor device. The edge of the opaque region terminates above the first isolation region. After exposure, the properties of the dual-tone resist allow a narrow sub-minimum width trench to be removed from the resist to define an isolation ring.

Abstract: High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.

Abstract: A low profile, metal shell insulation displacement contact (IDC) connector comprises an elongate insulative housing having two spaced longitudinally extending sidewalls and two transversely extending longitudinally spaced end walls. Within the interior of the housing sidewalls, there are a plurality of pockets formed therein for securing a metal shell to the housing. The metal shell is preferably made in two-part construction wherein a lower portion defining a continuous D-shaped configuration is attached by deformable tabs to an upper portion and the upper portion comprises a plurality of deformably prongs that are adapted to be received in the pockets of the housing and deformed therein for securing the composite metal shell thereto. A cover is latchably secured to the end walls of the housing and a strain relief is provided for sandwiching a flat multiconductor ribbon cable between the strain relief and the cover.

Abstract: An electrical connector for insulation displacment connection to conductors of a flat multiconductor cable includes an elongate insulative housing defining a cavity therein for latchably receiving a pair of insert subassemblies. During manufacture, each subassembly comprises a plurality of insulation displacement contacts having two, spaced tines defining therebetween a conductor receiving slot. Each contact is joined between adjacent tines by a carrier web to thereby form a joined array of contacts. An elongate insulative insert supports the contacts in each subassembly. Each insert has an upper surface defining a cable support surface from which the IDC ends project. A plurality of grooves extends into the insert upper surface, each groove being in substantial registry with a carrier web joining the tines. The grooves each have a bottom surface spaced from the carrier web. Such construction permits use of a suitable severing tool to remove the carrier webs in a ready manner with minimal wear on the tool.