Patents by Inventor James S. Dunn

James S. Dunn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7064416
    Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: June 20, 2006
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Louis D. Lanzerotti, Steven H. Voldman
  • Patent number: 7002221
    Abstract: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: February 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Marwan H. Khater, James S. Dunn, David L. Harame, Alvin J. Joseph, Qizhi Liu, Francois Pagette, Stephen A. St. Onge, Andreas D. Stricker
  • Patent number: 6906401
    Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Natalie B. Feilchenfeld, Qizhi Liu, Andreas D. Stricker
  • Patent number: 6900519
    Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: May 31, 2005
    Assignee: International Business Machines Corporation
    Inventors: Marc W. Cantell, James S. Dunn, David L. Harame, Robb A. Johnson, Louis D. Lanzerotti, Stephen A. St. Onge, Brian L. Tessier, Ryan W. Wuthrich
  • Patent number: 6891251
    Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: May 10, 2005
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, James S. Dunn, Michael D. Gordon, Mohammed Y. Hammad, Jeffrey B. Johnson, David C. Sheridan
  • Patent number: 6869854
    Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: March 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Marc W. Cantell, James S. Dunn, David L. Harame, Robb A. Johnson, Louis D. Lanzerotti, Stephen A. St. Onge, Brian L. Tessier, Ryan W. Wuthrich
  • Publication number: 20040222497
    Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Applicant: International Business Machines Corporation
    Inventors: James S. Dunn, Natalie B. Feilchenfeld, Qizhi Liu, Andreas D. Stricker
  • Publication number: 20040224461
    Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.
    Type: Application
    Filed: May 28, 2004
    Publication date: November 11, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James S. Dunn, Natalie B. Feilchenfeld, Qizhi Liu, Andreas D. Stricker
  • Publication number: 20040222495
    Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.
    Type: Application
    Filed: June 10, 2004
    Publication date: November 11, 2004
    Inventors: Marc W. Cantell, James S. Dunn, David L. Harama, Robb A. Johnson, Louis D. Lametotti, Stephen A. St. Onge, Brian L. Tessier, Ryan W. Wuthrich
  • Patent number: 6809024
    Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: October 26, 2004
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Natalie B. Feilchenfeld, Qizhi Liu, Andreas D. Stricker
  • Publication number: 20040092109
    Abstract: A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.
    Type: Application
    Filed: October 31, 2003
    Publication date: May 13, 2004
    Applicant: International Business Machines Corporation
    Inventors: Eric Adler, James S. Dunn, Joseph Iadanza, Jenifer E. Lary
  • Patent number: 6683345
    Abstract: A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: January 27, 2004
    Assignee: International Business Machines, Corp.
    Inventors: Eric Adler, James S. Dunn, Joseph Iadanza, Jenifer E. Lary, Kent E. Morrett, Josef S. Watts
  • Publication number: 20040014271
    Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.
    Type: Application
    Filed: July 18, 2002
    Publication date: January 22, 2004
    Applicant: International Business Machines Corporation
    Inventors: Marc W. Cantell, James S. Dunn, David L. Harame, Robb A. Johnson, Louis D. Lanzerotti, Stephen A. St. Onge, Brian L. Tessier, Ryan W. Wuthrich
  • Publication number: 20030122128
    Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.
    Type: Application
    Filed: December 18, 2002
    Publication date: July 3, 2003
    Applicant: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, James S. Dunn, Michael D. Gordon, Mohamed Y. Hammad, Jeffrey B. Johnson, David C. Sheridan
  • Publication number: 20030094673
    Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.
    Type: Application
    Filed: November 16, 2001
    Publication date: May 22, 2003
    Applicant: International Business Machines Corporation
    Inventors: James S. Dunn, Louis D. Lanzerotti, Steven H. Voldman
  • Patent number: 6521506
    Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: February 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, James S. Dunn, Michael D. Gordon, Mohamed Y. Hammad, Jeffrey B. Johnson, David C. Sheridan
  • Patent number: 6476483
    Abstract: In an electronic device with an active region on top of and isolated from an substrate, a first material region is defined on top of and/or adjacent to and electrically isolated from the active region and a second material region is attached to a surface of the first material region to form an interface defining a Peltier cooling junction therebetween. A current source connected in series to the first and the second material regions produces a cooling effect at the Peltier cooling junction.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: November 5, 2002
    Assignee: International Business Machines Corporation
    Inventors: Eric Adler, James S. Dunn, Kent E. Morrett, Edward J. Nowak, Stephen A. St. Onge
  • Patent number: 6448124
    Abstract: A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: September 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, James S. Dunn, Peter J. Geiss, Peter B. Gray, David L. Harame, Kathryn T. Schonenberg, Stephen A. St. Onge, Seshadri Subbanna
  • Patent number: 6420766
    Abstract: The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: July 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey S. Brown, James S. Dunn, Steven J. Holmes, David V. Horak, Robert K. Leidy, Steven H. Voldman
  • Publication number: 20020076874
    Abstract: A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.
    Type: Application
    Filed: November 12, 1999
    Publication date: June 20, 2002
    Inventors: DOUGLAS D. COOLBAUGH, JAMES S. DUNN, PETER J. GEISS, PETER B. GRAY, DAVID L. HARAME, KATHRYN T. SCHONENBERG, STEPHEN A. ST. ONGE, SESHADRI SUBBANNA