Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells and a fuse array configured to store precondition data. The precondition data can identify a portion of the memory array, specify a predetermined precondition state, or a combination thereof. When the memory device powers on, the memory device can be configured to automatically retrieve the precondition data from the fuse array and/or to write memory cells in the portion of the memory array to the predetermined precondition state before executing an access command.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data on which the pattern matching operation is performed may not be output from the memory during the pattern matching operation.

Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

Abstract: A memory device includes a memory bank that includes a first set of memory rows in a first section of the memory bank, a first set of redundant rows in a first section of the memory bank, a second set of memory rows in a second section of the memory bank, and a second set of redundant rows in the second section of the memory bank. The memory bank also includes a repeater blocker circuit that when in operation selectively blocks a signal from transmission to the second section of the memory bank and blocker control circuitry that when in operation transmits a control signal to control the selective blocking of the signal by the repeater blocker circuit.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.

Abstract: Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

Abstract: Methods, systems, and apparatuses related to determination of durations of memory device temperatures are described. For example, a controller can be coupled to a memory device to monitor an operating temperature of the memory device. The controller can determine the operating temperature exceeds a threshold temperature. The controller can determine a duration that the temperature exceeds the threshold temperature. The controller can provide data corresponding to the operating temperature and the duration to a requesting device.

Abstract: Dynamic trim selection based on operating voltage levels for semiconductor devices and associated methods and systems are disclosed. Certain semiconductor devices are expected to operate under two or more operating voltage levels. In some embodiments, the semiconductor device can be characterized to determine optimum timing and/or voltage conditions across multiple operating voltage levels. Consequently, multiple sets of timing and/or voltage conditions can be identified depending on the operating voltage levels, which can be stored in a non-volatile memory (NVM) array of the semiconductor device. During operation, the semiconductor device can determine the operating voltage level currently supplied to the semiconductor device and select one of the timing and/or voltage conditions stored in the NVM array such that the semiconductor device can operate with the optimum timing and/or voltage conditions that has been predetermined for the semiconductor device operating under the operating voltage level.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data on which the pattern matching operation is performed may not be output from the memory during the pattern matching operation.

Abstract: A memory device includes a memory bank that includes a first set of memory rows in a first section of the memory bank, a first set of redundant rows in a first section of the memory bank, a second set of memory rows in a second section of the memory bank, and a second set of redundant rows in the second section of the memory bank. The memory bank also includes a repeater blocker circuit that when in operation selectively blocks a signal from transmission to the second section of the memory bank and blocker control circuitry that when in operation transmits a control signal to control the selective blocking of the signal by the repeater blocker circuit.

Abstract: Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands. A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

Abstract: Dynamic trim selection based on operating voltage levels for semiconductor devices and associated methods and systems are disclosed. Certain semiconductor devices are expected to operate under two or more operating voltage levels. In some embodiments, the semiconductor device can be characterized to determine optimum timing and/or voltage conditions across multiple operating voltage levels. Consequently, multiple sets of timing and/or voltage conditions can be identified depending on the operating voltage levels, which can be stored in a non-volatile memory (NVM) array of the semiconductor device. During operation, the semiconductor device can determine the operating voltage level currently supplied to the semiconductor device and select one of the timing and/or voltage conditions stored in the NVM array such that the semiconductor device can operate with the optimum timing and/or voltage conditions that has been predetermined for the semiconductor device operating under the operating voltage level.

Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

Abstract: The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.

Abstract: Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.