Patents by Inventor James W. Tschanz

James W. Tschanz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10698432
    Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Yi-Chun Shih, Kaushik Mazumdar, Stephen T. Kim, Rinkle Jain, James W. Tschanz, Muhammad M. Khellah
  • Patent number: 10600462
    Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Shigeki Tomishima, James W. Tschanz, Shih-Lien L. Lu
  • Patent number: 10359834
    Abstract: Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Muhammad M. Khellah, James W. Tschanz
  • Patent number: 10297302
    Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Shigeki Tomishima, Wei Wu, Shih-Lien Lu, James W. Tschanz, Georgios Panagopoulos, Helia Naeimi
  • Patent number: 10024916
    Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: July 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
  • Patent number: 9948179
    Abstract: Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jaydeep P. Kulkarni, Pascal A. Meinerzhagen, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
  • Patent number: 9916884
    Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Charles Augustine, Carlos Tokunaga, James W. Tschanz
  • Patent number: 9870012
    Abstract: Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
  • Patent number: 9830988
    Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Wei Wu, Shigeki Tomishima, Shih-Lien L. Lu, James W. Tschanz
  • Publication number: 20170337958
    Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.
    Type: Application
    Filed: April 24, 2017
    Publication date: November 23, 2017
    Inventors: Charles AUGUSTINE, Shigeki TOMISHIMA, James W. TSCHANZ, Shih-Lien L. LU
  • Publication number: 20170322617
    Abstract: Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.
    Type: Application
    Filed: January 18, 2017
    Publication date: November 9, 2017
    Inventors: Subramaniam Maiyuran, Muhammad M. Khellah, James W. Tschanz
  • Patent number: 9805790
    Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Nathaniel J. August, Pulkit Jain, Stefan Rusu, Fatih Hamzaoglu, Rangharajan Venkatesan, Muhammad Khellah, Charles Augustine, Carlos Tokunaga, James W. Tschanz, Yih Wang
  • Patent number: 9772903
    Abstract: The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 26, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jaydeep P. Kulkarni, Keith A. Bowman, James W. Tschanz, Vivek K. De
  • Patent number: 9762241
    Abstract: Some embodiments include apparatus and methods using a first ring oscillator, a second ring oscillator, and circuit coupled to the first and second ring oscillators. The first ring oscillator includes a first memory cell and a first plurality of stages coupled to the first memory cell. The second ring oscillator includes a second memory cell and a second plurality of stages coupled to the second memory cell. The circuit includes a first input node coupled to an output node of the first ring oscillator and a second input node coupled to an output node of the second ring oscillator. In one of such embodiments, the circuit can operate to generate identification information to authenticate the apparatus.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Suriya Ashok Kumar, Carlos Tokunaga, James W. Tschanz
  • Patent number: 9722606
    Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply, the clamp including a plurality of transistors, a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode. The control unit includes a first comparator to compare the second power supply with a first reference, a second comparator to compare the second power supply with a second reference, and a counter. The counter counts up when the second power supply is higher than the first reference and counts down when the second power supply is lower than the second reference.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Arijit Raychowdhury, Charles Augustine, James W. Tschanz, Vivek K. De
  • Publication number: 20170178708
    Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.
    Type: Application
    Filed: December 6, 2016
    Publication date: June 22, 2017
    Inventors: Charles AUGUSTINE, Shigeki TOMISHIMA, Wei WU, Shih-Lien LU, James W. TSCHANZ, Georgios PANAGOPOULOS, Helia NAEIMI
  • Publication number: 20170178710
    Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.
    Type: Application
    Filed: March 7, 2014
    Publication date: June 22, 2017
    Inventors: Charles AUGUSTINE, Carlos TOKUNAGA, James W. TSCHANZ
  • Patent number: 9680472
    Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: June 13, 2017
    Assignee: INTEL CORPORATION
    Inventors: Amit R. Trivedi, Jaydeep P. Kulkarni, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz
  • Patent number: 9666257
    Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: May 30, 2017
    Assignee: INTEL CORPORATION
    Inventors: Charles Augustine, Shigeki Tomishima, James W. Tschanz, Shih-Lien L. Lu
  • Publication number: 20170139006
    Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
    Type: Application
    Filed: February 1, 2017
    Publication date: May 18, 2017
    Inventors: Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De