Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.

Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.

Abstract: A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.

Abstract: Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.

Abstract: A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.

Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.

Abstract: Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.

Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.

Abstract: A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.

Abstract: A system may include detection of a direction of transistor body current flow, and control of a regulator transistor to regulate a transistor body voltage based on the detected direction. In some aspects, a first regulator transistor is controlled if the direction of current flow is into a transistor body and a second regulator transistor is controlled if the direction of current flow is out of the transistor body.

Abstract: In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.

Abstract: Embodiments of the present invention provide a method, apparatus and system for dynamically adjusting one or more performance-related parameters of a processor core based on at least one operation parameter related to an operating condition of the processor core.

Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.

Abstract: A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths.

Abstract: A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.

Abstract: Apparatus and systems, as well as methods and articles, may operate to select a microprocessor clock frequency responsive to a desired voltage and/or a desired temperature of operation.

Abstract: A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.

Abstract: A method and apparatus for performing majority voting is presented. The method selects pairs of inputs, performs AND and NOR operations on each pair of inputs to determine that each pair of inputs is both high or both low, yielding a quantity of “both high” pairs and a quantity of “both low” pairs, and compares the quantity of “both high” pairs against the quantity of “both low” pairs to determine the majority. The apparatus includes AND gates configured to receive pairs of values and NOR gates configured to receive the same pairs of values, with a connections between all AND gates and connections between all NOR gates. A summation element sums all AND gate outputs and all NOR gate outputs to determine the majority.