Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.

Abstract: The invention relates to a transconductance amplifier, providing current variations di=k·dv when it receives voltage variations dv. The amplifier comprises a first MOS transistor (MN4) whose drain provides differential currents (I?di, I+di). It comprises an output stage having a second transistor (MP5) of a type opposite to the first, whose source is linked to the drain of the first, whose gate is biased at a constant potential (Vref), and whose drain receives the current variations which are provided by the first transistor and which must be applied to a sampling capacitor.

Abstract: The invention relates to sampled filters with finite impulse response, or FIR filters. According to the invention, there is proposed an FIR filter comprising a transconductance amplifier with controllable gain (AGM), at least one sampling capacitor (CE) intended to receive an output current (di) from the amplifier and to periodically accumulate the charges produced by N successive samples of this current, and means for controlling the gain of the amplifier to give the amplifier a desired individual gain for each of the N samples. The weighting of the coefficients of the finite impulse response filter is effected through the transconductance gain of the amplifier and not through the value of a capacitor.

Abstract: The invention relates to a transconductance amplifier, intended to supply current variations di when it receives voltage variations dv, with a desired conversion coefficient Gm called transconductance: Gm=di/dv. The amplifier comprises a PMOS transistor (MP1) and an NMOS transistor (MP2) connected by their drains, their gates both being connected to the voltage input receiving dv; the source of the first transistor is connected to a constant current source (IB1) and to a resistor (R) and to the drain of a third MOS transistor (MN3) of the same type as the first; the sources of the second (MN2) and third (MN3) transistors are commoned, the gate of the third transistor being connected to the drains of the first and second; the output is connected to a circuit (MN4) which mirrors the current of the third transistor. The resulting amplifier has good linearity and can be used in a sample and hold device used to sample charges.

Abstract: A low-phase noise voltage control oscillator (VCO) comprising a voltage source for supplying control voltage to the VCO core; a phase lock loop, having an output connected to an input of the voltage source; a VCO core, including an amplifier circuit with noiseless biasing and a tank circuit with noiseless biasing of the varactors; having an output connected to an input of the phase lock loop; and an attenuator, located between the voltage source and the VCO core, for reducing phase noise from the voltage source to the VCO core.

Abstract: A pin electronics circuit for use in automatic testing equipment that includes a load for testing a pin of a device under test. The load of the pin electronics circuit is electrically coupled to a precision parametric measurement unit. In this embodiment, the precision pin measurement unit provides a forcing signal to the load when a high current mode is desired. In response to the forcing signal, the load generates a current through a resistor that results in a desired current or voltage at a pin of the device under test. Since the load is used in high current mode, the precision parametric measurement unit does not include a high current output stage.

Abstract: In one embodiment of the invention, a switchable output current mirror with feedback is disclosed. The current mirror includes a master stage, a slave stage, and an operational amplifier that is coupled in a feedback loop with the master stage. A reference current is introduced at an input node of the current mirror. The input node is coupled to an input terminal of the operational amplifier and to a current source of the master stage. The output of the operational amplifier electrically couples to the master stage to control the current source of the master stage. The slave stage of the current mirror includes a current source that receives the output from the output terminal of the operational amplifier to control the current source. The slave stage also includes a switch for receiving a control signal and selectively coupling the current source of the slave stage with the output of the current mirror. The master stage may include a switch that is controllable by a control signal.

Abstract: A circuit operating as a bridgeless current load in pin testing equipment for testing a pin of a device under test is disclosed. The circuit includes a transconductance stage having at least a first input and a second input and at least one output capable of being coupled to a pin of a device under test. The circuit further includes a first limiting current source coupled to the transconductance stage for sourcing the pin of the device under test to a first current level and a second limiting current source coupled to the transconductance stage for sinking the pin of the device under test to a second current level. The first input receives a commutation voltage and the second input receives a voltage at the output of the transconductance stage from the device under test. When the output voltage is above the commutation voltage, the first limiting current source is active and when the output voltage is below the commutation voltage, the second limiting current source is active.

Abstract: A network device may provide secure fallback operations. The device includes a port allowing the device to communicate with a network and a processor to generate a security credential, provide the security credential to a call manager during initialization, and provide the security credential to a secondary device during fallback operations. The network device may include a memory to store the security credential and routing information for fallback operations.

Abstract: A low-phase noise voltage control oscillator (VCO) comprising a voltage source for supplying control voltage to the VCO core; a phase lock loop, having an output connected to an input of the voltage source; a VCO core, including an amplifier circuit with noiseless biasing and a tank circuit with noiseless biasing of the varactors; having an output connected to an input of the phase lock loop; and an attenuator, located between the voltage source and the VCO core, for reducing phase noise from the voltage source to the VCO core.

Abstract: An integrated circuit logic topology or architecture suitable for low voltage differential logic operating at radio frequencies is disclosed. The topology, referred to as enhanced pseudo common mode logic, is similar to and compatible with traditional CML, and provides the additional advantage of eliminating the need for level conversion between consecutive logic gates, thereby increasing the potential maximum operating frequency of subsystems implemented using the invention. The invention retains most of the advantages of traditional CML, and in addition permits the independent selection of output logic high level and output logic low level so that they may be matched with the succeeding circuit input levels.

Abstract: An integrated circuit logic topology or architecture suitable for low voltage differential logic operating at radio frequencies is disclosed. The topology, referred to as enhanced pseudo common mode logic, is similar to and compatible with traditional CML, and provides the additional advantage of eliminating the need for level conversion between consecutive logic gates, thereby increasing the potential maximum operating frequency of subsystems implemented using the invention. The invention retains most of the advantages of traditional CML, and in addition permits the independent selection of output logic high level and output logic low level so that they may be matched with the succeeding circuit input levels.

Abstract: A valve assembly for controlling the amount of coolant exiting an engine is provided. The valve assembly includes a valve housing that is mounted to the engine and defines a passage that is in fluid communication with a coolant outlet in the engine. A motor in the valve housing drives a valve shaft that extends into the passage and on which a butterfly valve plate is mounted. The physical geometry of the inventive assembly is not significantly effected by changes in coolant temperature or coolant contamination and the integrates the valve member and actuator in a single assembly to improve packaging and material use and eliminates potential coolant leak points.

Abstract: A system for associating an audit history with a database form is disclosed. In one embodiment of the present invention, a database document is displayed on a first portion of a display on network client computer. An audit history is displayed on a second portion of the display. The audit history contains information describing the transmission history of the document and any action taken with regard to the document. The audit history is updated automatically as the document is transmitted from one user to another user in the network.