Patents by Inventor James Wilson Rose

James Wilson Rose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6671948
    Abstract: An interconnection structure includes: a dielectric layer; a first metallization pattern on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; a cured adhesive on a portion of the dielectric layer, the adhesive not present in an area aligned with the at least one etch stop; and at least one electrical device being attached to the dielectric layer by the adhesive such that an active area of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optional additional portion of cured adhesive, the additional portion of the cured adhesive being adhesively attached to the dielectric layer and not adhesively attached to the at least one electrical device.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: January 6, 2004
    Assignee: General Electric Company
    Inventors: William Edward Burdick, Jr., James Wilson Rose, Kevin Matthew Durocher, Raymond Albert Fillion
  • Publication number: 20030146401
    Abstract: A two-stage valve for controlling the flow of fluid from a pressurized fluid supply with an upper main body including a cavity with a contoured inner surface; a lower main body with at least one flow exhaust passage forming a primary flow path through the two-stage valve; a pre-stressed diaphragm sandwiched between the upper and lower main bodies, and pressure control capability for controlling the pressure in the cavity. A first valve opens and closes the flow of gas from the pressurized gas supply to the cavity. A second valve allows the pressure in the cavity to exhaust to the environment. Raising and lowering of the pressure in the cavity causes the pre-stressed diaphragm to open and close the flow of gas from the pressurized gas supply through the primary flow path of the two-stage valve. The design is suitable as a microvalve using Micro-Electro-Mechanical Systems (MEMS) concepts.
    Type: Application
    Filed: February 28, 2003
    Publication date: August 7, 2003
    Applicant: Lockheed Martin Corporation
    Inventors: Todd Garrett Wetzel, Mathew Christian Nielsen, Stanton Earl Weaver, Renato Guida, James Wilson Rose, Laura Jean Meyer
  • Patent number: 6602739
    Abstract: A method for making a multichip “HDI” module includes the step of making a substrate for supporting the semiconductor or solid-state chips (or other components) by applying electrical conductor in a pattern to a first dielectric sheet, and applying encapsulating material to the electrical conductor. Apertures are made in the first dielectric sheet and encapsulant at locations at which the chips (or other components) are to be located. The components are affixed to a second dielectric sheet at locations registered with the apertures in the first sheet, and the sheets are juxtaposed with the chips extending into the apertures. This results in the formation of gaps between the components and the edges of the apertures, which gaps are then filled with hardenable or curable material. Electrical connection is made to the pads of the chips by means of a multilayer structure of dielectric sheets with conductor patterns, interconnected by means of plated-through vias.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: August 5, 2003
    Assignee: Lockheed Martin Corporation
    Inventors: James Wilson Rose, Thomas Bert Gorczyca, Christopher James Kapusta, Ernest Wayne Balch, Kevin Matthew Durocher
  • Patent number: 6557820
    Abstract: A two-stage valve for controlling the flow of gas from a pressurized gas supply with an upper main body including a cavity; a lower main body with at least one flow exhaust passage forming a primary flow path through the two-stage valve; a pre-stressed diaphragm sandwiched between the upper and lower main bodies, and pressure control capability for controlling the pressure in the cavity. A secondary flow path exists from the pressurized gas supply through the lower main body, through the upper main body, and terminating in the cavity in the upper main body. A first valve is installed in the secondary flow path to open and close the flow of gas from the pressurized gas supply to the cavity. A second valve installed in an exhaust passage in the upper main body allows the pressure in the cavity to exhaust to the environment. When the second valve is closed, the pressure in the cavity in the upper main body can be increased to lower the pre-stressed diaphragm.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: May 6, 2003
    Assignee: Lockheed Martin Corporation
    Inventors: Todd Garrett Wetzel, Matthew Christian Nielsen, Stanton Earl Weaver, Jr., Renato Guida, James Wilson Rose, Laura Jean Meyer
  • Patent number: 6548329
    Abstract: A hard layer of amorphous hydrogenated carbon (DLC) overlies a polymer film structure and a plurality of soft layers of DLC alternate with a plurality of hard layers of DLC over the barrier base to form a corrosion resistant structure. The polymer film structure and a circuit chip can be elements of a circuit module. The DLC and the polymer film structure can have vias extending to contact pads, and a pattern of electrical conductors can extend through the vias to the contact pads. In one embodiment the DLC forms a hermetic (and therefore corrosion resistant) seal over the polymer film structure.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: April 15, 2003
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, James Wilson Rose
  • Publication number: 20020197767
    Abstract: A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost.
    Type: Application
    Filed: July 22, 2002
    Publication date: December 26, 2002
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, James Wilson Rose, Leonard Richard Douglas
  • Publication number: 20020180351
    Abstract: UV reflectors incorporated in UV LED-based light sources reduce the amount of UV radiation emission into the surroundings and increase the efficiency of such light sources. UV reflectors are made of nanometer-sized particles having a mean particle diameter less than about one-tenth of the wavelength of the UV light emitted by the UV LED, dispersed in a molding or casting material surrounding the LED. Other UV reflectors are series of layers of materials having alternating high and low refractive indices; each layer has a physical thickness of one quarter of the wavelength divided by the refractive index of the material. Nanometer-sized textures formed on a surface of the multilayered reflector further reduce the emission of UV radiation into the surroundings. UV LED-based light sources include such a multilayered reflector disposed on an encapsulating structure of a transparent material around a UV LED, particles of a UV-excitable phosphor dispersed in the transparent material.
    Type: Application
    Filed: April 30, 2001
    Publication date: December 5, 2002
    Inventors: Thomas Francis McNulty, Daniel Darcy Doxsee, James Wilson Rose
  • Publication number: 20020175302
    Abstract: A two-stage valve for controlling the flow of gas from a pressurized gas supply with an upper main body including a cavity; a lower main body with at least one flow exhaust passage forming a primary flow path through the two-stage valve; a pre-stressed diaphragm sandwiched between the upper and lower main bodies, and pressure control capability for controlling the pressure in the cavity. A secondary flow path exists from the pressurized gas supply through the lower main body, through the upper main body, and terminating in the cavity in the upper main body. A first valve is installed in the secondary flow path to open and close the flow of gas from the pressurized gas supply to the cavity. A second valve installed in an exhaust passage in the upper main body allows the pressure in the cavity to exhaust to the environment. When the second valve is closed, the pressure in the cavity in the upper main body can be increased to lower the pre-stressed diaphragm.
    Type: Application
    Filed: May 22, 2001
    Publication date: November 28, 2002
    Applicant: Lockeheed Martin Corporation
    Inventors: Todd Garrett Wetzel, Matthew Christian Nielsen, Stanton Earl Weaver, Renato Guida, James Wilson Rose, Laura Jean Meyer
  • Patent number: 6475877
    Abstract: A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: November 5, 2002
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, James Wilson Rose, Leonard Richard Douglas
  • Patent number: 6417062
    Abstract: A method of forming a ruthenium dioxide film for such purposes as the fabrication of stable thin-film resistors for microcircuits. The method generally entails forming an inorganic ruthenium-based film on a substrate, and then thermally decomposing at least a portion of the ruthenium-based film by exposure to a high-intensity beam of radiation, preferably visible light, to yield a ruthenium dioxide film on the substrate. Particular ruthenium-based precursors useful for forming the ruthenium-based film include ruthenium (III) chloride (RuCl3.nH2O) and ruthenium (III) nitrosyl nitrate. The method does not require a thermal treatment that heats the bulk of the substrate on which the ruthenium dioxide film is formed, and is therefore suitable for non-ceramic substrate materials, e.g., polymers such as those used as printed circuit boards (PCBs) and flexible circuits.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: July 9, 2002
    Assignee: General Electric Company
    Inventors: Donald Franklin Foust, James Wilson Rose, Ernest Wayne Balch
  • Publication number: 20020075107
    Abstract: An interconnection structure includes: a dielectric layer; a first metallization pattern on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; a cured adhesive on a portion of the dielectric layer, the adhesive not present in an area aligned with the at least one etch stop; and at least one electrical device being attached to the dielectric layer by the adhesive such that an active area of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optional additional portion of cured adhesive, the additional portion of the cured adhesive being adhesively attached to the dielectric layer and not adhesively attached to the at least one electrical device.
    Type: Application
    Filed: December 18, 2000
    Publication date: June 20, 2002
    Inventors: William Edward Burdick, James Wilson Rose, Kevin Matthew Durocher, Raymond Albert Fillion
  • Patent number: 6239482
    Abstract: An integrated circuit package includes at least one integrated circuit element coupled to a polymer film; a window frame coupled to the polymer film and surrounding the at least one integrated circuit element; and encapsulant material positioned between the at least one integrated circuit element and the window frame.
    Type: Grant
    Filed: June 21, 1999
    Date of Patent: May 29, 2001
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, William Edward Burdick, Jr., Ronald Frank Kolc, James Wilson Rose, Glenn Scott Claydon
  • Patent number: 6177237
    Abstract: A method for fabricating a substantially transparent polymer substrate for an anti-scatter x-ray grid for medical diagnostic radiography includes positioning a phase mask between the substrate and a high power laser; providing a laser beam from the laser; conditioning the laser beam; ablating a first portion the substrate through the phase mask with the conditioned laser beam; and moving the substrate; and ablating a second portion of the substrate through the phase mask with the conditioned laser beam.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: January 23, 2001
    Assignee: General Electric Company
    Inventors: Renato Guida, James Wilson Rose, Kenneth Paul Zarnoch, Gary John Thumann
  • Patent number: 6150719
    Abstract: A hard layer of amorphous hydrogenated carbon (DLC) overlies a polymer film structure and a plurality of soft layers of DLC alternate with a plurality of hard layers of DLC over the barrier base to form a corrosion resistant structure. The polymer film structure and a circuit chip can be elements of a circuit module. The DLC and the polymer film structure can have vias extending to contact pads, and a pattern of electrical conductors can extend through the vias to the contact pads. In one embodiment the DLC forms a hermetic (and therefore corrosion resistant) seal over the polymer film structure.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: November 21, 2000
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, James Wilson Rose
  • Patent number: 6040226
    Abstract: A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: March 21, 2000
    Assignee: General Electric Company
    Inventors: Robert John Wojnarowski, James Wilson Rose, Ernest Wayne Balch, Leonard Richard Douglas, Evan Taylor Downey, Michael Gdula
  • Patent number: 5897728
    Abstract: For fully testing and burning-in an integrated circuit chip before it is incorporated into a high density interconnect or other standard hybrid bare chip circuit, a temporary test substrate having pins extending therethrough holds the chip within a cavity. Chip pads are electrically connected with the pins to create a package that can be tested using commercially available testing and burn-in devices. After testing, the chip is retrieved from the test structure undamaged. In using HDI techniques to interconnect the chip with the pins, metal-filled vias in a polymer layer overlying the temporary test substrate electrically connect the chip to the pins through a metal interconnect pattern on the polymer layer. In another embodiment, the chip is interconnected with the pins through wire bonds. Metal-filled vias pass through an insulative coating on the chip and make electrical contact with the chip pad.
    Type: Grant
    Filed: September 6, 1991
    Date of Patent: April 27, 1999
    Assignee: Lockheed Martin Corporation
    Inventors: Herbert Stanley Cole, James Wilson Rose, Robert John Wojnarowski, Charles William Eichelberger
  • Patent number: 5872040
    Abstract: A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: February 16, 1999
    Assignee: General Electric Company
    Inventors: Robert John Wojnarowski, James Wilson Rose, Ernest Wayne Balch, Leonard Richard Douglas, Evan Taylor Downey, Michael Gdula
  • Patent number: 5849623
    Abstract: A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: December 15, 1998
    Assignee: General Electric Company
    Inventors: Robert John Wojnarowski, James Wilson Rose, Kyung Wook Paik, Michael Gdula
  • Patent number: 5757072
    Abstract: A protective cap is deposited over the top and sides of an air bridge structure located on an integrated circuit chip. The protective cap provides mechanical strength during the application of a high density interconnect structure over the chips, to prevent deformation of the sensitive (air bridge) structure, and also to prevent any contamination from intruding under the air bridge. More importantly, the protective cap does not impede the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure. Furthermore, the protective cap allows additional area for metallization to provide alternate circuits for coupling, power or ground planes, etc.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: May 26, 1998
    Assignee: Martin Marietta Corporation
    Inventors: Bernard Gorowitz, Charles Adrian Becker, Renato Guida, Thomas Bert Gorczyca, James Wilson Rose
  • Patent number: 5683928
    Abstract: A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: November 4, 1997
    Assignee: General Electric Company
    Inventors: Robert John Wojnarowski, James Wilson Rose, Ernest Wayne Balch, Leonard Richard Douglas, Evan Taylor Downey, Michael Gdula