Abstract: A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base.

Abstract: A solar cell array is described which can be designed in particular as a thin-film solar module. A production method for a solar cell array is further described.

Abstract: Solar module arrays are described, including a solar module for photovoltaic energy generation, a connection housing connected to the solar module for connecting the solar module to an electric load, and a free-wheeling diode connected antiparallel to the solar module. A diode cable is also described.

Abstract: An integrated circuit includes an array of resistance changing memory cells, and a circuit configured to apply an initialization signal to a first one of the memory cells that is in a virgin resistance state. The initialization signal is configured to modify the first memory cell without switching an operation state of the first memory cell.

Abstract: According to one embodiment of the present invention, a method of operating an integrated circuit including a plurality of resistance changing memory cells grouped into physical memory units is provided. The method includes: Monitoring writing access numbers assigned to the physical memory units, each writing access number reflecting the number of writing accesses to the physical memory unit to which the writing access number is assigned; if the value of a writing access number assigned to a first physical memory unit exceeds a writing access threshold value, a data exchange process is carried out during which the data content stored within the first physical memory unit is exchanged with the data content of a second physical memory unit having a writing access number of a lower value.

Abstract: An integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory element and the heater.

Abstract: A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.

Abstract: A memory cell includes a first electrode, a second electrode, and phase change material between the first electrode and the second electrode. The phase change material has a step-like programming characteristic. The first electrode, the second electrode, and the phase change material form a via or trench memory cell.

Abstract: An integrated circuit is fabricated by providing a preprocessed wafer including a first electrode, depositing a dielectric material over the preprocessed wafer, etching an opening in the dielectric material to expose a portion of the first electrode and depositing a first resistivity changing material over exposed portions of the etched dielectric material and the first electrode. The first resistivity changing material is planarized to expose the etched dielectric material. A second resistivity changing material is deposited over the etched dielectric material and the first resistivity changing material, and an electrode material is deposited over the second resistivity changing material.

Abstract: A memory cell includes a first electrode, a storage location, and a second electrode. The storage location includes a phase change material and contacts the first electrode. The storage location has a first cross-sectional width. The second electrode contacts the storage location and has a second cross-sectional width greater than the first cross-sectional width. The first electrode, the storage location, and the second electrode form a pillar phase change memory cell.

Abstract: An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material.

Abstract: An integrated circuit includes a bit line, a plurality of access devices coupled to the bit line, and a plate of phase change material. The integrated circuit includes a plurality of phase change elements contacting the plate of phase change material and a plurality of first contacts. Each first contact is coupled between an access device and a phase change element.

Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material including a first portion contacting the first electrode, a second portion contacting the second electrode, and a third portion between the first portion and the second portion. A width of the third portion is less than a width of the first portion and a width of the second portion.

Abstract: A memory cell includes a first electrode, a second electrode, and a first portion of phase-change material contacting the first electrode. The memory cell includes a second portion of phase-change material contacting the second electrode and a third portion of phase-change material between the first portion and the second portion. A phase-change material composition of the third portion and the second portion gradually transitions from the third portion to the second portion.

Abstract: A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

Abstract: An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse.

Abstract: A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse.

Abstract: An embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element. The element includes at least one bottom electrode; at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; and at least one heater layer on at least a portion of an upper surface of the phase change material layer, wherein the heater layer has a tapered shape such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.

Abstract: An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.

Abstract: A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse.