Patents by Inventor Jan Boris Philipp

Jan Boris Philipp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT AND METHOD FOR SWITCHING A RESISTIVELY SWITCHING MEMORY CELL
    Publication number: 20090285014
    Abstract: An integrated circuit and method for switching a resistively switching memory cell. One embodiment provides an initial pulse and at least one escalated pulse in case the memory cell did not switch.
    Type: Application
    Filed: May 15, 2008
    Publication date: November 19, 2009
    Applicant: Qimonda AG
    Inventors: Petra Majewski, Jan Boris Philipp
  • INTEGRATED CIRCUIT WITH AN ARRAY OF RESISTANCE CHANGING MEMORY CELLS
    Publication number: 20090285007
    Abstract: An integrated circuit includes an array of resistance changing memory cells, and a circuit configured to apply an initialization signal to a first one of the memory cells that is in a virgin resistance state. The initialization signal is configured to modify the first memory cell without switching an operation state of the first memory cell.
    Type: Application
    Filed: May 16, 2008
    Publication date: November 19, 2009
    Inventors: Petra Majewski, Jan Boris Philipp
  • Memory cell with trigger element
    Patent number: 7619917
    Abstract: A memory device includes a plurality of word lines extending as rows and bit lines extending as columns. A memory cell is coupled between a word line and a bit line, wherein the memory cell includes a unipolar memory element selectively coupled to the bit line via a trigger element.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: November 17, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Philipp
  • System that prevents reduction in data retention
    Patent number: 7619936
    Abstract: One embodiment of the present invention provides a system including a tester and a back end manufacturing system. The tester tests a resistive memory and obtains configuration data for the resistive memory. The back end manufacturing system prevents temperatures in back end processing from reducing data retention time of the configuration data in the resistive memory.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: November 17, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ
  • Integrated circuit having an insulated memory
    Patent number: 7615770
    Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material between the first electrode and the second electrode. The phase-change material defines a narrow region. The memory cell includes first insulation material having a first thermal conductivity and contacting the phase-change material. A maximum thickness of the first insulation material contacts the narrow region. The memory cell includes a second insulation material having a second thermal conductivity greater than the first thermal conductivity and contacting the first insulation material.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: November 10, 2009
    Assignee: Infineon Technologies AG
    Inventors: Jan Boris Philipp, Thomas Happ, Renate Bergmann
  • MEMORY DEVICE WITH DIFFERENT TYPES OF PHASE CHANGE MEMORY
    Publication number: 20090268513
    Abstract: A memory includes a first memory device including an array of phase changing memory cells. The first memory device is of a first memory type. The integrated circuit includes a second memory device including an array of phase changing memory cells. The second memory device is of a second memory type that is different than the first memory type. The first and second memory devices are packaged together into a single memory device.
    Type: Application
    Filed: April 29, 2008
    Publication date: October 29, 2009
    Inventors: Luca De Ambroggi, Jan Boris Philipp, Peter Schroegmeier, Gernot Steinlesberger, Christian Pho Duc, Franz Kreupl
  • Integrated circuit having resistive memory cells
    Patent number: 7601995
    Abstract: A memory includes an array of memory cells, each memory cell including resistive material, a first insulation material laterally surrounding the resistive material of each memory cell, and a heat spreader between the memory cells to thermally isolate each memory cell.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: October 13, 2009
    Assignee: Infineon Technologies AG
    Inventors: Thomas Happ, Ulrike Gruening-von Schwerin, Jan Boris Philipp
  • MEMORY CELL HAVING IMPROVED MECHANICAL STABILITY
    Publication number: 20090251944
    Abstract: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion and the base portion having respective outer surfaces and the pillar portion having a width less than that of the base portion. A memory element is on a top surface of the pillar portion of the bottom electrode, and a top electrode is on the memory element. A dielectric spacer contacts the outer surface of the pillar portion, the outer surface of the base portion of the bottom electrode self-aligned with an outer surface of the dielectric spacer.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Applicant: Macronix International Co., Ltd.
    Inventors: Thomas D Happ, Yi-Chou Chen, Jan Boris Philipp, Hsiang-Lan Lung
  • INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT DOPED WITH DIELECTRIC MATERIAL
    Publication number: 20090237983
    Abstract: An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 24, 2009
    Applicant: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Integrated circuit for programming a memory element
    Patent number: 7593255
    Abstract: An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element by iteratively applying a variable program pulse to the memory element until a resistance of the memory element crosses a first reference resistance. The variable program pulse is adjusted for each iteration such that the resistance of the memory element approaches the first reference resistance.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: September 22, 2009
    Assignees: Qimonda North America Corp., Infineon Technologies AG
    Inventors: Thomas Happ, Thomas Nirschl, Jan Boris Philipp
  • Memory including write circuit for providing multiple reset pulses
    Patent number: 7577023
    Abstract: An integrated circuit includes an array of resistive memory cells having varying critical dimensions and a write circuit. The write circuit is configured to reset a selected memory cell by applying a first pulse having a first amplitude and a second pulse having a second amplitude less than the first amplitude to the selected memory cell.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: August 18, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ, Thomas Nirschl
  • Circuit for programming a memory element
    Patent number: 7571901
    Abstract: An integrated circuit includes a memory element and a circuit. The circuit is configured to program the memory element by applying one or more pulses to the memory element until a sensed resistance of the memory element is within a range of a desired resistance. The one or more pulses have a parameter value that is modified for each subsequent pulse based on the parameter value for an immediately preceding pulse and on a difference between the sensed resistance of the memory element and the desired resistance.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: August 11, 2009
    Assignee: Qimonda North America Corp.
    Inventor: Jan Boris Philipp
  • ERROR CORRECTION IN AN INTEGRATED CIRCUIT WITH AN ARRAY OF MEMORY CELLS
    Publication number: 20090199043
    Abstract: An integrated circuit includes an array of memory cells, and an error correction code circuit configured to correct errors in data read from the array based at least in part on a map that identifies locations of erratic memory cells in the array.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Inventors: Peter Schrogmeier, Jan Boris Philipp, Thomas Happ, Luca DeAmbroggi, Christian Pho Duc, Franz Kreupl, Gernot Steinlesberger
  • STACKED DIE MEMORY
    Publication number: 20090196093
    Abstract: A memory includes a first die including a first array of phase change memory cells and a second die including a second array of phase change memory cells. The second die is stacked above the first die. The memory includes lines configured to access the first die and the second die. The first die and the second die are enclosed in a single package.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Applicant: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Circuit for programming a memory element
    Patent number: 7564710
    Abstract: An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: July 21, 2009
    Assignees: Qimonda North America Corp., Macronix International Co., Ltd.
    Inventors: Thomas Happ, Jan Boris Philipp, Ming-Hsiu Lee
  • INTEGRATED CIRCUIT FOR SETTING A MEMORY CELL BASED ON A RESET CURRENT DISTRIBUTION
    Publication number: 20090161415
    Abstract: An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Applicant: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ, Bernhard Ruf, Christian Ruster, Dieter Andres, Petra Majewski
  • Resistive memory having shunted memory cells
    Patent number: 7551476
    Abstract: A memory includes a bit line and a plurality of resistive memory cells coupled to the bit line. Each resistive memory cell is programmable to each of at least three resistance states. The memory includes a first resistor for selectively coupling to the bit line to form a first current divider with a selected memory cell during a read operation.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: June 23, 2009
    Assignees: Qimonda North America Corp., Qimonda AG
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Philipp
  • INTEGRATED CIRCUIT INCLUDING QUENCH DEVICES
    Publication number: 20090154226
    Abstract: An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 18, 2009
    Applicant: Qimonda North America Corp.
    Inventors: Thomas Happ, Jan Boris Philipp
  • INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS
    Publication number: 20090154227
    Abstract: The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 18, 2009
    Inventors: Jan Boris Philipp, Thomas Happ
  • Integrated circuit having a switch
    Patent number: 7548448
    Abstract: A reprogrammable switch includes a first phase-change element, a first reference element, and a second reference element. The switch includes a sense amplifier for outputting a first signal based on a comparison of a signal from the first phase-change element to a signal from the first reference element and for outputting a second signal based on a comparison of the signal from the first phase-change element to a signal from the second reference element.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: June 16, 2009
    Assignee: Infineon Technologies AG
    Inventors: Jan Boris Philipp, Thomas Happ