Abstract: A device includes a fault generation circuit and a first fault injection circuit. The fault generation circuit is configured to generate a fault signal and a plurality of control signals according to a mode signal. The first fault injection circuit is configured to inject a first final fault signal to an under-test device based on the fault signal and the plurality of control signals, in order to verify robustness of the under-test device.

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.

Abstract: Disclosed herein is a method for treating and/or preventing atrial fibrillation in a subject, comprising administering to the subject a pharmaceutical composition comprising an anti-CD44 neutralizing antibody or an antigen binding portion thereof which specifically binds to the amino-terminal domain of CD44. The anti-CD44 neutralizing antibody is a monoclonal antibody. The pharmaceutical composition further includes a pharmaceutically acceptable carrier.

Abstract: A transformer circuit and a manufacturing method thereof are proposed. The transformer circuit includes plural input modules and output modules. Each of the input modules includes a first primary coil and a second primary coil, and each of the primary coils has a first positive input terminal and a negative input terminal. The first primary coil and the second primary coil of each of the input modules are inductively coupled with each other. Each of the output modules includes a secondary coil. Each of the secondary coils includes a first terminal and a second terminal. The first terminal and the second terminal of each of the secondary coils are electrically connected to a first output port and a second output port, respectively. The first primary coil and the second primary coil of each of the input modules are inductively coupled to the secondary coil of the corresponding output module, respectively.

Abstract: A method for diagnosing a defect is provided. A first candidate pair comprises a first defect candidate and a second defect candidate. A first pattern is generated to distinguish one or more faults of the first defect candidate from one or more faults of the second defect candidate. The first defect candidate is removed responsive to determining that the first pattern does not detect the first defect candidate and determining that an automatic test equipment (ATE) failure log associates the first pattern with failure. Removing the first candidate pair, as well as additional candidate pairs when possible, promotes diagnosis efficiency by reducing a number of computations required.

Abstract: An Allen wrench structure contains: at least one operating segment formed on a gripping handle and having plural hexagonal cross-sectional faces, wherein the at least one operating segment has a first cross-sectional face and a second cross-sectional face. A diameter L1 of an inscribed circle of the first cross-sectional face is less than a diameter L2 of an inscribed circle of the second cross-sectional face, and a working part of the at least one operation segment between the first cross-sectional face and the second cross-sectional face is conical. A misalignment angle ?1 is defined between the first cross-sectional face and the second cross-sectional face so that among six vertices of the first cross-sectional face and six vertices of the second cross-sectional face are defined six extending edges, and each extending edge is defined between each vertex of the first cross-sectional face and each vertex of the second cross-sectional face.

Abstract: Disclosed herein is a method for treating and/or preventing atrial fibrillation in a subject, comprising administering to the subject a pharmaceutical composition comprising an anti-CD44 neutralizing antibody or an antigen binding portion thereof which specifically binds to the amino-terminal domain of CD44. The anti-CD44 neutralizing antibody is a monoclonal antibody. The pharmaceutical composition further includes a pharmaceutically acceptable carrier.

Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.

Abstract: A transformer circuit and a manufacturing method thereof are proposed. The transformer circuit includes plural input modules and output modules. Each of the input modules includes a first primary coil and a second primary coil, and each of the primary coils has a first positive input terminal and a negative input terminal. The first primary coil and the second primary coil of each of the input modules are inductively coupled with each other. Each of the output modules includes a secondary coil. Each of the secondary coils includes a first terminal and a second terminal. The first terminal and the second terminal of each of the secondary coils are electrically connected to a first output port and a second output port, respectively. The first primary coil and the second primary coil of each of the input modules are inductively coupled to the secondary coil of the corresponding output module, respectively.

Abstract: A modulation method includes sampling the first input signal by using the first local oscillation signal and the second local oscillation signal to generate the first sampled signal, sampling the second input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the second sampled signal, sampling the second input signal by using the first local oscillation signal and the second local oscillation signal to generate the third sampled signal, sampling the first input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the fourth sampled signal, adding the first sampled signal and the second sampled signal to produce the first modulation signal, adding the third sampled signal and the fourth sampled signal to generate the second modulation signal, and adding the first modulation signal and the second modulation signal to generate an output signal.

Abstract: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).

Abstract: An RF reflectometry scanning tunneling microscope is suitable for observing a surface of an object, and includes a probe that cooperates with the object to form a tunneling resistor therebetween, an RF resonant circuit that cooperates with the tunneling resistor to form a LCR resonant circuit including an inductor connected to a parallel connection of a capacitor, a resistor and the tunneling resistor, a directional coupler receiving an RF signal and outputting the RF signal to the LCR resonant circuit, and an RF signal measuring device that generates a scanning result associated with the surface of the object based on a reflected RF signal resulting from reflection of the RF signal by the LCR resonant circuit.

Abstract: A power converter control circuit includes a feedback circuit and a pulse width modulation signal generating circuit for configuring a power stage circuit to provide power to a load. The feedback circuit generates a first gain signal and a second gain signal according to an output voltage sensing signal coupled with the load. The feedback circuit further generates a feedback signal according to the first gain signal and the second gain signal. The pulse width modulation signal generating circuit configures the operation of the power stage circuit according to the feedback signal and a reference signal. Moreover, the feedback circuit and the pulse width modulation signal generating circuit are configured on the same integrated circuit package.

Abstract: A method for diagnosing a defect is provided. A first candidate pair comprises a first defect candidate and a second defect candidate. A first pattern is generated to distinguish one or more faults of the first defect candidate from one or more faults of the second defect candidate. The first defect candidate is removed responsive to determining that the first pattern does not detect the first defect candidate and determining that an automatic test equipment (ATE) failure log associates the first pattern with failure. Removing the first candidate pair, as well as additional candidate pairs when possible, promotes diagnosis efficiency by reducing a number of computations required.

Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.

Abstract: A modulation method includes sampling the first input signal by using the first local oscillation signal and the second local oscillation signal to generate the first sampled signal, sampling the second input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the second sampled signal, sampling the second input signal by using the first local oscillation signal and the second local oscillation signal to generate the third sampled signal, sampling the first input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the fourth sampled signal, adding the first sampled signal and the second sampled signal to produce the first modulation signal, adding the third sampled signal and the fourth sampled signal to generate the second modulation signal, and adding the first modulation signal and the second modulation signal to generate an output signal.

Abstract: A multi-functional lock may include a main body, a control unit, a connecting unit and a securing unit. The multi-functional lock is advantageous because the main body uses the connecting unit to control the securing unit and control unit, and a rod and a locking unit are independent components, so when the user is conducting a forcefully unlocking process, only the rod is damaged without damaging the main body and the rod can be easily replaced.

Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.