Patents by Inventor Jan Chen
Jan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150121065Abstract: In a method of protecting copyright of a digital media file in an electronic device, the electronic device receives a request for downloading the digital media file, from a recipient electronic device, the electronic device requires the recipient electronic device, to provide information of the recipient electronic device, the electronic device further requests a third-party authorization system, to allocate a key for the digital media file according to the information, once the electronic device locks the digital media file using the key, the electronic device sends the locked digital media file to the recipient electronic device.Type: ApplicationFiled: October 24, 2013Publication date: April 30, 2015Applicant: CHIUN MAI COMMUNICATION SYSTEMS, INC.Inventor: CHO-JAN CHEN
-
Publication number: 20150026847Abstract: An RF reflectometry scanning tunneling microscope is suitable for observing a surface of an object, and includes a probe that cooperates with the object to form a tunneling resistor therebetween, an RF resonant circuit that cooperates with the tunneling resistor to form a LCR resonant circuit including an inductor connected to a parallel connection of a capacitor, a resistor and the tunneling resistor, a directional coupler receiving an RF signal and outputting the RF signal to the LCR resonant circuit, and an RF signal measuring device that generates a scanning result associated with the surface of the object based on a reflected RF signal resulting from reflection of the RF signal by the LCR resonant circuit.Type: ApplicationFiled: September 19, 2014Publication date: January 22, 2015Applicant: National Taiwan UniversityInventors: Woei-Wu PAI, Huan-Hsin LI, I-Jan CHEN, Yen-Cheng CHAO
-
Publication number: 20140354535Abstract: The invention proposes a system and method of a display device. When the distance between a user and the display device is too close or far, or the angle between the user and the display device slants too much, the display device sends out a command to inform the user to adjust the user's position while watching the display device. A method for the display device comprises following steps: a detecting device and an operating system calculating a relative position between the user and the display device, the operating system generating an warning command according to the relative position, a warning module receiving the warning command and afterward sending out the command, the command being sent to a display module, a motion-generating device and an audio device.Type: ApplicationFiled: August 28, 2013Publication date: December 4, 2014Inventors: TAI-JAN CHEN, SHOU-MEI XIE, YI-JAN CHEN
-
Patent number: 8903359Abstract: In a near-field communication (NFC) service protection method of the mobile device, the mobile device includes an NFC controller, one or more security elements, a global positioning system (GPS) and a storage system. The method sets a security code for an NFC service of each of the security elements according to the geographic location of the mobile device as acquired by the GPS, and stores a security protection of the NFC service corresponding to each of the NFC services into the storage system. After an NFC service is selected from one of the security elements, and the NFC service is performed by executing an NFC application corresponding to the NFC service through the NFC controller. In addition, the method deletes the security code of the NFC service to disable the security protection of the NFC service when the NFC service needs to disable the security protection.Type: GrantFiled: March 27, 2012Date of Patent: December 2, 2014Assignee: Chi Mei Communication Systems, Inc.Inventors: Cho-Jan Chen, Li-Yun Chen
-
Patent number: 8863062Abstract: Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.Type: GrantFiled: July 9, 2012Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lin Chuang, Ji-Jan Chen, Ching-Fang Chen, Yun-Han Lee
-
Patent number: 8863311Abstract: An RF reflectometry scanning tunneling microscope is suitable for observing a surface of an object, and includes a probe that cooperates with the object to form a tunneling resistor therebetween, an RF resonant circuit that cooperates with the tunneling resistor to form a LCR resonant circuit including an inductor connected to a parallel connection of a capacitor, a resistor and the tunneling resistor, an RF signal generator that outputs an RF signal via a directional coupler to the LCR resonant circuit, and an RF signal measuring device that generates a scanning result associated with the surface of the object based on a reflected RF signal resulting from reflection of the RF signal by the LCR resonant circuit.Type: GrantFiled: September 25, 2013Date of Patent: October 14, 2014Assignee: National Taiwan UniversityInventors: Woei-Wu Pai, Huan-Hsin Li, I-Jan Chen
-
Publication number: 20140253084Abstract: A power converter control circuit includes a feedback circuit and a pulse width modulation signal generating circuit for configuring a power stage circuit to provide power to a load. The feedback circuit generates a first gain signal and a second gain signal according to an output voltage sensing signal coupled with the load. The feedback circuit further generates a feedback signal according to the first gain signal and the second gain signal. The pulse width modulation signal generating circuit configures the operation of the power stage circuit according to the feedback signal and a reference signal. Moreover, the feedback circuit and the pulse width modulation signal generating circuit are configured on the same integrated circuit package.Type: ApplicationFiled: March 11, 2014Publication date: September 11, 2014Applicant: Richtek Technology CorporationInventors: Ching-Jan CHEN, Shao-Hung LU, Jian-Rong HUANG
-
Patent number: 8832511Abstract: A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.Type: GrantFiled: August 15, 2011Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ji-Jan Chen, Nan-Hsin Tseng, Chin-Chou Liu
-
Patent number: 8707238Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.Type: GrantFiled: May 31, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Yi-Lin Chuang, Cheng-Pin Chiu, Ching-Fang Chen, Ji-Jan Chen, Sandeep Kumar Goel, Yun-Han Lee, Charles C. C. Liu
-
Patent number: 8693967Abstract: A receiver of a GNSS system is provided. The receiver comprises two mixers and a processing circuit. The first mixer down-converts an input radio-frequency signal comprising a first GNSS signal and a second GNSS signal into a first low-frequency signal. The second mixer down-converts the input radio-frequency signal into a second low-frequency signal. The processing circuit generates at least one phase-shifted low-frequency signal according to at least the first low-frequency signal, extract signal components of the first GNSS signal by rejecting signal components of the second GNSS signal according to the second low-frequency signal and the at least one phase-shifted low-frequency signal, and extract signal components of the second GNSS signal by rejecting signal components of the first GNSS signal according to the second low-frequency signal and the at least one phase-shifted low-frequency signal. The first and second GNSS signals are situated in different frequency ranges.Type: GrantFiled: March 28, 2011Date of Patent: April 8, 2014Assignees: Mediatek Inc., National Taiwan UniversityInventors: Chi-Wei Cheng, Yueh-Hua Yu, Yi-Jan Chen
-
Publication number: 20140049281Abstract: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Ling Liu, Nan-Hsin Tseng, Ji-Jan Chen, Wei-Pin Changchien, Samuel C. Pan
-
Patent number: 8614571Abstract: Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.Type: GrantFiled: November 18, 2011Date of Patent: December 24, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Saurabh Gupta, Ji-Jan Chen, Chi Wei Hu
-
Publication number: 20130326463Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Cheng-Pin Chiu, Ching-Fang Chen, Ji-Jan Chen, Sandeep Kumar Goel, Yun-Han Lee, Charles C.C. Liu
-
Publication number: 20130290914Abstract: Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.Type: ApplicationFiled: July 9, 2012Publication date: October 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Lin Chuang, Ji-Jan Chen, Ching-Fang Chen, Yun-Han Lee
-
Patent number: 8525497Abstract: For a multiphase interleaved voltage regulator, an offset cancellation circuit is applied for each phase separately. The current loop gain of each phase is thus increased to mitigate the beat-frequency oscillation in phase currents when the beat frequency is below the bandwidth of the low-pass filter in the offset cancellation circuit, without introducing additional instability issue that is the drawback of increasing current-sensing gain.Type: GrantFiled: February 1, 2011Date of Patent: September 3, 2013Assignee: Rickhtek Tecnology Corp.Inventors: Chen-Hua Chiu, Ching-Jan Chen, Dan Chen, Wei-Hsu Chang
-
Publication number: 20130127441Abstract: Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Hsin TSENG, Chin-Chou LIU, Saurabh GUPTA, Ji-Jan CHEN, Chi Wei HU
-
Publication number: 20130054653Abstract: A method of constructing a database for etching profile is disclosed. First, a standard etching group including a standard etching structure and a deviated etching group including a deviated etching structure are provided. Second, a remote sensing (RS) step is carried out to collect a standard RS data belonging to the standard etching group and a deviated RS data belonging to the deviated etching group. Then, the RS data is analyzed to infer feature parameters of the etching groups. Next, a deviated physical parameter is verified. Later, the correlation between the feature parameters and the deviated physical parameter is calculated to construct an etching profile database including the standard RS data and the deviated RS data. The etching profile database may facilitate the prediction of an unknown etching profile.Type: ApplicationFiled: October 6, 2011Publication date: February 28, 2013Inventors: Ming-Tsung Hsu, Chun-Chi Chen, Hao-Jan Chen
-
Patent number: 8384455Abstract: An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.Type: GrantFiled: May 23, 2011Date of Patent: February 26, 2013Assignee: Industrial Technology Research InstituteInventors: Yu Lee, Nai-Chen Cheng, Ji-Jan Chen, Yuan-Hua Chu, Ching-Yuan Yang
-
Publication number: 20130047049Abstract: A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.Type: ApplicationFiled: August 15, 2011Publication date: February 21, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ji-Jan CHEN, Nan-Hsin Tseng, Chin-Chou Liu
-
Patent number: 8360828Abstract: A cutting tool suitable for cutting a workpiece placed on a photocurable adhesive layer is provided. The cutting tool includes a main body, a cutting layer and a light emitting material. The cutting layer is disposed on a surface of the main body and is applicable in cutting the workpiece. The light emitting material is disposed inside the cutting layer or between the main body and the cutting layer. The light emitting material is suitable for emitting a light capable of curing the photocurable adhesive layer adjacent to a cutting path as the workpiece is cut by the cutting layer.Type: GrantFiled: September 3, 2010Date of Patent: January 29, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jan-Chen Huang, Chu-Ching Sung, Ming-Yu Huang