Abstract: A phosphate-free automatic dishwashing cleaning composition including: a) a protease wherein the protease is a variant having at least 60% identity with the amino acid sequence of SEQ ID NO:1 or SEQ ID NO:2 including two negatively charged amino acid residues, aspartic acid (D) and/or glutamic acid (E), in positions 124-131 using the SEQ ID NO: 1 numbering and the SEQ ID NO:2, respectively; and b) from 10 to 50% by weight of the composition of a complexing agent system comprising from 0 to less than 30% by weight of the composition of citric acid.

Abstract: An apparatus includes a transmitter circuit coupled to a termination resistor. The transmitter circuit generates a number of link pulses. A driver circuit is coupled to the transmitter circuit to control a dynamic range of the link pulses. A transformer couples the termination resistor via a transmission medium to a far-end transceiver. The driver circuit controls the dynamic range of the link pulses by providing complementary digital input signals to the transmitter circuit, and the complementary digital input signals include ramp sections.

Abstract: A wireless transmitter processing chain includes digital radio frequency mixing circuitry to generate, in digital form, a representation of a transmit signal including multiple communication channels. From the digital representation, a wideband digital to analog converter creates the analog transmit signal that includes the communication channels. Individual mixers and filters follow, with mixing frequencies tuned to place the communication channels at the desired frequency centers.

Abstract: A digital-to-analog converter (DAC) includes a plurality of segments, wherein the plurality of segments includes a first segment electronically coupled to each of the plurality of segments, wherein the first segment includes a predetermined number of most significant bits (MSB), a second segment electronically coupled to each of the plurality of segments, wherein the second segment includes a first predetermined number of least significant bits (LSB), and a third segment electronically coupled with each of the plurality of segments, wherein the third segment includes a second predetermined number of LSBs. Additionally, the DAC includes an all logic implementation.

Abstract: A wireless transmitter processing chain includes digital radio frequency mixing circuitry to generate, in digital form, a representation of a transmit signal including multiple communication channels. From the digital representation, a wideband digital to analog converter creates the analog transmit signal that includes the communication channels. Individual mixers and filters follow, with mixing frequencies tuned to place the communication channels at the desired frequency centers.

Abstract: A wireless transmitter processing chain includes digital radio frequency mixing circuitry to generate, in digital form, a representation of a transmit signal including multiple communication channels. From the digital representation, a wideband digital to analog converter creates the analog transmit signal that includes the communication channels. Individual mixers and filters follow, with mixing frequencies tuned to place the communication channels at the desired frequency centers.

Abstract: A wireless transmitter processing chain includes digital radio frequency mixing circuitry to generate, in digital form, a representation of a transmit signal including multiple communication channels. From the digital representation, a wideband digital to analog converter creates the analog transmit signal that includes the communication channels. Individual mixers and filters follow, with mixing frequencies tuned to place the communication channels at the desired frequency centers.

Abstract: A device for digitally protecting against an overvoltage event may include a front-end circuit, an overvoltage protection circuit, and a protection switch. The protection switch may be coupled to the overvoltage protection circuit and may be configured to decouple the front-end circuit from an external medium, in response to a clamp signal. The overvoltage protection circuit may be configured to detect the overvoltage event at one or more nodes of a circuit. In response to the detection of the overvoltage event, the overvoltage protection circuit may generate the clamp signal to activate the protection switch.

Abstract: A decoder for a current-steering digital-to-analog converter (DAC) is described herein. In an embodiment, the decoder is a dynamic element matching (DEM) row/column decoder that randomizes pairs of row control signals and column control signals that are provided to a matrix of current cells. The randomization is performed in a manner that ensures that the pairs of row control signals are randomized as pairs. In another embodiment, the decoder is an N-dimensional decoder, where N is any integer greater than two. The N-dimensional decoder comprises an N number of decoders that are each configured to provide respective control signals that are provided to current source(s) in current cell(s) in a respective dimension of an N-dimensional matrix of current cells for enabling current source(s) included therein. Such decoders advantageously allow for a simpler, more efficient design compared to a non-segmented, unary DAC due to the smaller area and lower power consumed.

Abstract: A parallel sample-and-hold circuit includes a sampling switch and a hold capacitor for each of the ADC and MDAC of a converter stage for a pipelined ADC. Each sampling switch couples the analog input of the first converter stage to its hold capacitor at the time a sample is desired to be taken. After the sample is placed on the hold capacitor, the sampling switch is opened and the hold capacitor stores the sample. To compensate for mismatches in the signal paths of these sample-and-hold circuits, a compensation switch is further used. The compensation switch couples the terminals of the hold capacitors together, creating a parallel sample-and-hold circuit. The compensation switch is controlled such that it is closed after the sampling switches are opened to equalize a voltage of the samples.

Abstract: A decoder for a current-steering digital-to-analog converter (DAC) is described herein. In an embodiment, the decoder is a dynamic element matching (DEM) row/column decoder that randomizes pairs of row control signals and column control signals that are provided to a matrix of current cells. The randomization is performed in a manner that ensures that the pairs of row control signals are randomized as pairs. In another embodiment, the decoder is an N-dimensional decoder, where N is any integer greater than two. The N-dimensional decoder comprises an N number of decoders that are each configured to provide respective control signals that are provided to current source(s) in current cell(s) in a respective dimension of an N-dimensional matrix of current cells for enabling current source(s) included therein. Such decoders advantageously allow for a simpler, more efficient design compared to a non-segmented, unary DAC due to the smaller area and lower power consumed.

Abstract: A device for gain calibration of an analog-to-digital converter (ADC) residue amplifier includes a digital-to analog converter (DAC) configured to convert a digital signal to an analog signal. The DAC includes a calibration capacitor that can be used in the gain calibration of the ADC residue amplifier. A flash ADC, including a plurality of comparators and an additional comparator, generates the digital signal. The additional comparator provides a threshold voltage approximately in a middle point of a nominal subrange. The nominal subrange comprises a portion of a voltage range corresponding to threshold voltages of two adjacent comparators of the plurality of comparators.

Abstract: A parallel sample-and-hold circuit includes a sampling switch and a hold capacitor for each of the ADC and MDAC of a converter stage for a pipelined ADC. Each sampling switch couples the analog input of the first converter stage to its hold capacitor at the time a sample is desired to be taken. After the sample is placed on the hold capacitor, the sampling switch is opened and the hold capacitor stores the sample. To compensate for mismatches in the signal paths of these sample-and-hold circuits, a compensation switch is further used. The compensation switch couples the terminals of the hold capacitors together, creating a parallel sample-and-hold circuit. The compensation switch is controlled such that it is closed after the sampling switches are opened to equalize a voltage of the samples.

Abstract: A device for gain calibration of an analog-to-digital converter (ADC) residue amplifier includes a digital-to analog converter (DAC) configured to convert a digital signal to an analog signal. The DAC includes a calibration capacitor that can be used in the gain calibration of the ADC residue amplifier. A flash ADC, including a plurality of comparators and an additional comparator, generates the digital signal. The additional comparator provides a threshold voltage approximately in a middle point of a nominal subrange. The nominal subrange comprises a portion of a voltage range corresponding to threshold voltages of two adjacent comparators of the plurality of comparators.

Abstract: A system may include a first stage comprising first signaling components for a first protocol, and a second stage comprising second signaling components for the first protocol and a second protocol. The system may further include logic configured to receive an incoming data stream, and determine a stream protocol for the data stream. The logic may be further configured to, responsive to the determination, activate the at least a portion of the first stage when the stream protocol is compliant with the first protocol, and when the stream protocol is compliant with the second protocol, deactivate the first stage.

Abstract: A device for digitally protecting against an overvoltage event may include a front-end circuit, an overvoltage protection circuit, and a protection switch. The protection switch may be coupled to the overvoltage protection circuit and may be configured to decouple the front-end circuit from an external medium, in response to a clamp signal. The overvoltage protection circuit may be configured to detect the overvoltage event at one or more nodes of a circuit. In response to the detection of the overvoltage event, the overvoltage protection circuit may generate the clamp signal to activate the protection switch.

Abstract: The invention relates to a device for coating substrates having a process chamber (1) disposed in a reactor housing and a two-part, substantially cup-shaped susceptor (2, 3) disposed therein, forming an upper susceptor part (2) with the cup floor thereof having a flat plate (2?) and a lower susceptor part (3) with the cup side walls thereof, the outer side (4) of the plate (2?) of the upper susceptor part (2) facing upwards toward the process chamber (1) and forming a contact surface for at least one substrate, the upper susceptor part (2) contacting a front edge (3?) of the lower susceptor part (3) at the edge of said upper susceptor part (2), the lower susceptor part (3) being supported by a susceptor carrier (6), and heating zones (A, B, C) for heating the upper susceptor part (2) being disposed below the plate (2?).

Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.

Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.