Abstract: An electronic device includes a substrate, and a stack of dies stacked on the substrate. The stack includes (i) multiple dies stacked on one another, the multiple dies include electronic components and interconnections, and (ii) one or more heat pipes (HPs), which are traversing at least a subset of the dies at a right angle relative to the substrate, at least one of the HPs being configured to dissipate heat generated by operation of the electronic components away from at least the subset of the dies.

Abstract: An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

Abstract: An electronic device, including a substrate and a stack of dies stacked on the substrate. The stack of dies includes: (a) one or more functional dies, the functional dies including functional electronic circuits and being configured to exchange electrical signals at least with the substrate, and (b) one or more dummy dies, the dummy dies being disposed among dies forming the stack and being configured to: (i) dissipate heat generated by the one or more functional dies and (ii) pass electrical signals exchanged between the substrate and the one or more functional dies or between two or more of the functional dies.

Abstract: A method for assembling at least one stacked substrate package, each stacked substrate package includes binding a laminated base substrate, configured to route interconnections between circuitry on a first surface of the laminated base substrate and circuitry on a second surface of the laminated base substrate, to a surface of a rigid carrier to prevent warping of the laminated base substrate. Each base substrate is coupled to at least one dielectric build-up substrate, which is configured to route integrated interconnections between a top surface and a bottom surface of the dielectric build-up substrate, to the laminated base substrate. At least one integrated circuit die is coupled to the at least one dielectric build-up substrate, and then the carrier is released from the laminated base substrate to form an assembled stacked substrate package. Also, multiple stacked substrate packages may be assembled in parallel on one carrier.

Abstract: An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

Abstract: An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract: An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.

Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract: Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins extending from the first base. The first base comprises a cutout therein and a first base bottom surface contacting a first electronic component. A second heat sink comprises a second base and fins extending from the second base. The second heat sink is located in the cutout of the first heat sink. The second base comprises a second base bottom surface contacting a second electronic component. A pressure plate is attached to the first heat sink and overlays the second heat sink. The pressure plate contacts the second heat sink and applies pressure between the second heat sink and the second electronic component.

Abstract: Heat spreader lids and package assemblies including a heat spreader lid. The heat spreader lid has a central region configured to be coupled with an electronic component, a peripheral region configured to be coupled with a substrate, and a connecting region arranged between the central region and the peripheral region. The connecting region is configured to impart stress relief to the central region.

Abstract: Heat spreader lids and package assemblies including a heat spreader lid. The heat spreader lid has a central region configured to be coupled with an electronic component, a peripheral region configured to be coupled with a substrate, and a connecting region arranged between the central region and the peripheral region. The connecting region is configured to impart stress relief to the central region.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract: Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins extending from the first base. The first base comprises a cutout therein and a first base bottom surface contacting a first electronic component. A second heat sink comprises a second base and fins extending from the second base. The second heat sink is located in the cutout of the first heat sink. The second base comprises a second base bottom surface contacting a second electronic component. A pressure plate is attached to the first heat sink and overlays the second heat sink. The pressure plate contacts the second heat sink and applies pressure between the second heat sink and the second electronic component.

Abstract: Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins extending from the first base. The first base comprises a cutout therein and a first base bottom surface contacting a first electronic component. A second heat sink comprises a second base and fins extending from the second base. The second heat sink is located in the cutout of the first heat sink. The second base comprises a second base bottom surface contacting a second electronic component. A pressure plate is attached to the first heat sink and overlays the second heat sink. The pressure plate contacts the second heat sink and applies pressure between the second heat sink and the second electronic component.

Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.