Abstract: There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

Abstract: There is provided a magnetic memory device and a method of forming the same. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.

Abstract: A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

Abstract: There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line.

Abstract: A method of writing to magnetic random access memory (MRAM) devices is provided. The method includes preparing a digit line disposed on a semiconductor substrate, a bit line crossing over the digit line, and a magnetic tunnel junction (MTJ) interposed between the digit line and the bit line. The MTJ has a pinned layer, a tunneling insulating layer, and a synthetic anti-ferromagnetic (SAF) free layer which are sequentially stacked. In addition, the SAF free layer has a bottom free layer and a top free layer which are separated by an exchange spacer layer. An initial magnetization state of the MTJ is read and compared with a desired magnetization state. When the initial magnetization state is different from the desired magnetization state, a first write line pulse is applied to one of the digit line and the bit line, and a second write line pulse is applied to the other of the digit line and the bit line, thereby changing the magnetization state of the MTJ.

Abstract: Provided are methods for forming conductive plug structures, such as via plugs, from a plurality of conductive layer patterns and methods of fabricating semiconductor devices, including semiconductor memory devices such as phase change semiconductor memory devices. An example method forms a small via structure by forming a conductive layer on a semiconductor substrate. A molding insulating layer is formed on the conductive layer and a via hole is formed through the insulating layer to expose a region of the conductive layer. A first via filling layer is formed and then partially removed to form a partial via plug. The formation and removal of the phase change material layer are then repeated as necessary to form a multilayer plug structure that substantially fills the via hole with the multilayer structure typically exhibiting reduced defects and damage than plug structures prepared by conventional methods.

Abstract: A method of sputtering to deposit a target material onto a substrate includes supplying an ionized gas to the substrate and the target material. A first DC bias voltage having a polarity opposite that of the ionized gas is applied to the target material to attract ions theretoward. A second DC bias voltage having a polarity opposite that of the first DC bias voltage is intermittently applied to the target material to reduce ion accumulation thereon. Related apparatus and methods of fabricating phase-changeable memory devices are also discussed.

Abstract: A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the contact plug may provide electrical connection between the magnetic tunnel junction structure and the semiconductor substrate, and the contact plug may be between the magnetic tunnel junction structure and the semiconductor substrate. Related methods are also discussed.

Abstract: An apparatus for depositing a thin film on a substrate includes a housing, a substrate support portion, a securing member, a heater, a target member and a plasma generator. The housing defines a process chamber. The substrate support portion is disposed in the process chamber to support the substrate. The securing member is adapted to non-electrically secure the substrate to the substrate support portion during performance of a process. The heater is provided to maintain the substrate supported by the substrate support portion at a process temperature. The target member faces the substrate support portion and includes materials to be deposited on the substrate. The plasma generator is adapted to excite a process gas supplied into the process chamber into a plasma state.

Abstract: In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.

Abstract: Provided are magnetic tunnel junction structures having bended tips at both ends thereof, magnetic RAM cells employing the same and photo masks used in formation thereof. The magnetic tunnel junction structures have a pinned layer pattern, a tunneling insulation layer pattern and a free layer pattern, which are stacked on an integrated circuit substrate. At least the free layer pattern has a main body as well as first and second bended tips each protruded from both ends of the main body when viewed from a plan view.

Abstract: A magnetic random access memory (MRAM), and a method of manufacturing the same, includes a switching device and a magnetic tunneling junction (MTJ) cell connected to the switching device, wherein the MTJ cell includes a pinned film having a metal film and a magnetic film, the magnetic film enclosing the metal film.

Abstract: There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

Abstract: A magnetic tunnel junction device includes a magnetically programmable free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.

Abstract: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

Abstract: A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

Abstract: In a method of forming a quantum dot having nanometeric size and a method of forming a gate electrode including the quantum dot, a first layer including a first material is deposited on the substrate. The first material has first atoms that are superbundant and bound with the weak bonding energy in the first layer. A second layer is deposited on the first layer. The second layer comprises a second material including second atoms that are capable of migrating into the first atoms. The first atoms are migrated into the second layer and the second atoms are migrated into the first layer, so that the second atoms are arranged in the first layer. Each of the second atoms in the first layer is formed into a quantum dot. An electrode layer is formed on the first layer after partially etching the second layer, and then a gate electrode is formed by patterning the electrode layer.

Abstract: In a method of forming a quantum dot having nanometeric size and a method of forming a gate electrode including the quantum dot, a first layer including a first material is deposited on the substrate. The first material has first atoms that are superbundant and bound with the weak bonding energy in the first layer. A second layer is deposited on the first layer. The second layer comprises a second material including second atoms that are capable of migrating into the first atoms. The first atoms are migrated into the second layer and the second atoms are migrated into the first layer, so that the second atoms are arranged in the first layer. Each of the second atoms in the first layer is formed into a quantum dot. An electrode layer is formed on the first layer after partially etching the second layer, and then a gate electrode is formed by patterning the electrode layer.

Abstract: A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.