Abstract: A computer system includes memory hardware configured to store structured microservice configuration data having multiple microservice entries each associated with one of multiple microservice applications of a request processing architecture. The system includes processor hardware configured to access structured microservice configuration data to identify the microservice applications of the request processing architecture, subscribing to messages transmitted by the identified microservice applications for event monitoring, and receiving multiple messages transmitted by the identified microservice applications.

Abstract: The present technology relates to compounds, kits, compositions, and methods useful for the treatment of numerous pathologies including dementia, Alzheimer's disease, Parkinson's disease, amyotrophic lateral sclerosis, and other neurodegenerative diseases, spinal cord injury, traumatic brain injury, diabetes and metabolic syndrome, defective wound healing, and/or sensorineural hearing and vision loss.

Abstract: A computer system includes memory hardware configured to store structured microservice configuration data having multiple microservice entries each associated with one of multiple microservice applications of a request processing architecture. The system includes processor hardware configured to access structured microservice configuration data to identify the microservice applications of the request processing architecture, subscribing to messages transmitted by the identified microservice applications for event monitoring, and receiving multiple messages transmitted by the identified microservice applications.

Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.

Abstract: An example device includes a memory that includes a first portion and a second portion, memory control circuitry structured to receive a first set of data associated with a first radar chirp, receive a second set of data associated with a second radar chirp, store a first subset of the first set of data in the first portion of the memory, store a first subset of the second set of data in the first portion of the memory adjacent to the first subset of the first set of data, and store a second subset of the first set of data and a second subset of the second set of data in the second portion of the memory.

Abstract: Systems and methods are provided for testing driver assistance components and systems. Testing may involve using different types of data received at different virtual channel ports of a serial interface, in which each port receives a particular type of data, which data are then routed to different destination components using a table mapping each virtual channel port to a particular destination component. In another aspect, an update packet is used to modify a current version of the table, which maps each virtual channel port of a set of virtual channel ports to at least one of multiple destination components, to generate an updated version of the table, which is then used for routing subsequently received packets. A data modification module (DMM), which is one of the multiple destination components, may be used in the update process.

Abstract: A cabinet and an access mechanism for the cabinet is disclosed. The cabinet may comprise of a door to access the interior. The door and the adjacent coplanar may be mounted movable jointed combination of first type of frames and second type of frames with telescopic slides and/or guide roller assemblies disposed between to impart the freedom of motion in the desired direction upon a suitable actuation. The first type of frames have been provided with an ability to pivot. The pivots being vertical axillar elements. The arrangement of the two types of frames with pivoted vertical axis provides a plurality of assemblies or shelves mounted on respective door and coplanar portion. The shelves are displaced angularly and laterally owing to the actuating mechanism of the door. The assemblies or shelves are interconnected using coupling elements, horizontal arms and a multiplicity of pivot points arranged at pre-determined distances.

Abstract: A method includes receiving first data at a controller of an ADAS via a first virtual channel of a camera serial interface 2 (CSI-2) data interface. The method also includes receiving second data at the controller of the ADAS via a second virtual channel of the CSI-2 data interface. The method includes storing the first data at a first address in a memory, the first address specified by the first virtual channel. The method also includes storing the second data at a second address of a control register, the control register specified by the second data. The method includes performing a test using the first data and the second data.

Abstract: A non-transitory computer-readable medium stores instructions executable by a processor to process data from a radar circuit having multiple antennas.

Abstract: A non-transitory computer-readable medium stores instructions executable by a processor to process data from a radar circuit having multiple antennas.

Abstract: A non-transitory computer-readable medium stores instructions that cause processors to obtain an N×M range matrix comprising radar data indexed by velocity and antenna and an M×S steering matrix comprising expected phases indexed by antenna and hypothesis angle. For each unique X×Y range slice corresponding to a particular set of X velocities, processors store the particular range slice in a first buffer. For each unique Y×Z steering slice corresponding to a particular set of Y antenna, processors store the particular steering slice in a second buffer. The processors perform beamforming operations on the range, steering, and intermediate slices, storing the result in a third buffer as the intermediate slice. After each steering and range slice for the particular set of X velocities has been iterated through, the processors store the intermediate slice as a beamforming slice for the particular set of X velocities and the hypothesis angles.

Abstract: A computer system includes memory hardware configured to store structured microservice configuration data having multiple microservice entries each associated with one of multiple microservice applications of a request processing architecture. The system includes processor hardware configured to access structured microservice configuration data to identify the microservice applications of the request processing architecture, subscribing to messages transmitted by the identified microservice applications for event monitoring, and receiving multiple messages transmitted by the identified microservice applications.

Abstract: Methods, apparatus, and systems to replace values in a device are disclosed. An example apparatus includes a processor and a replacement generator coupled to the processor and configured to detect an access, by the processor, of a first instruction at a first address in a first memory, in response to the detected access, compare the first address to a set of trigger instruction address records in a second memory, wherein the set of trigger instruction address records includes a first trigger instruction address record that is associated with a first replacement address record and a first replacement value record, and based on the first address corresponding to the first trigger instruction address record, replace a first value at a second address in a third memory specified by the first replacement address record with a second value specified by the first replacement value record.

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.

Abstract: A cabinet and an access mechanism for the cabinet is disclosed. The cabinet may comprise of a door to access the interior. The door and the adjacent coplanar may be mounted movable jointed combination of first type of frames and second type of frames with telescopic slides and/or guide roller assemblies disposed between to impart the freedom of motion in the desired direction upon a suitable actuation. The first type of frames have been provided with an ability to pivot. The pivots being vertical axillar elements. The arrangement of the two types of frames with pivoted vertical axis provides a plurality of assemblies or shelves mounted on respective door and coplanar portion. The shelves are displaced angularly and laterally owing to the actuating mechanism of the door. The assemblies or shelves are interconnected using coupling elements, horizontal arms and a multiplicity of pivot points arranged at pre-determined distances.

Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.

Abstract: A non-transitory computer-readable medium stores instructions that cause processors to obtain an N×M range matrix comprising radar data indexed by velocity and antenna and an M×S steering matrix comprising expected phases indexed by antenna and hypothesis angle. For each unique X×Y range slice corresponding to a particular set of X velocities, processors store the particular range slice in a first buffer. For each unique Y×Z steering slice corresponding to a particular set of Y antenna, processors store the particular steering slice in a second buffer. The processors perform beamforming operations on the range, steering, and intermediate slices, storing the result in a third buffer as the intermediate slice. After each steering and range slice for the particular set of X velocities has been iterated through, the processors store the intermediate slice as a beamforming slice for the particular set of X velocities and the hypothesis angles.

Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.

Abstract: Methods, apparatus, and systems to replace values in a device are disclosed. An example apparatus includes a processor and a replacement generator coupled to the processor and configured to detect an access, by the processor, of a first instruction at a first address in a first memory, in response to the detected access, compare the first address to a set of trigger instruction address records in a second memory, wherein the set of trigger instruction address records includes a first trigger instruction address record that is associated with a first replacement address record and a first replacement value record, and based on the first address corresponding to the first trigger instruction address record, replace a first value at a second address in a third memory specified by the first replacement address record with a second value specified by the first replacement value record.