Abstract: An example device includes a memory that includes a first portion and a second portion, memory control circuitry structured to receive a first set of data associated with a first radar chirp, receive a second set of data associated with a second radar chirp, store a first subset of the first set of data in the first portion of the memory, store a first subset of the second set of data in the first portion of the memory adjacent to the first subset of the first set of data, and store a second subset of the first set of data and a second subset of the second set of data in the second portion of the memory.

Abstract: A method for managing tasks performable by autonomous vehicles includes performing a setup for various utility capabilities of an autonomous vehicle, where the various utility capabilities of the autonomous vehicles perform multiple activities to complete a task. The method also includes receiving programming constructs to support task definitions and configurations of the various utility capabilities of the autonomous vehicle. The method also includes configuring the autonomous vehicle with the multiple activities to complete the task and associating each activity with one or more utility capabilities from the various utility capabilities of the autonomous vehicle. The method also includes instructing the autonomous vehicle to perform the multiple activities to complete the task and validating, via the various utility capabilities of the autonomous vehicle, the completion of the task.

Abstract: Systems and methods are provided for testing driver assistance components and systems. Testing may involve using different types of data received at different virtual channel ports of a serial interface, in which each port receives a particular type of data, which data are then routed to different destination components using a table mapping each virtual channel port to a particular destination component. In another aspect, an update packet is used to modify a current version of the table, which maps each virtual channel port of a set of virtual channel ports to at least one of multiple destination components, to generate an updated version of the table, which is then used for routing subsequently received packets. A data modification module (DMM), which is one of the multiple destination components, may be used in the update process.

Abstract: Systems and methods for visualization monitoring data from a cloud-based system include obtaining the monitoring data, wherein the monitoring data is based on transactions associated with a plurality of users of the cloud-based system; providing a Graphical User Interface (GUI); obtaining a plurality of filter selections for a plurality of filter types; and displaying a visualization comprising a Sankey diagram of the monitoring data with nodes in the Sankey diagram including each of the plurality of filter types and links between the nodes indicative of the transactions in the monitoring data. The monitoring data can be for one or more of cloud security service transactions, application access via a Zero Trust Network Access (ZTNA) service, and user experience metrics.

Abstract: A cabinet and an access mechanism for the cabinet is disclosed. The cabinet may comprise of a door to access the interior. The door and the adjacent coplanar may be mounted movable jointed combination of first type of frames and second type of frames with telescopic slides and/or guide roller assemblies disposed between to impart the freedom of motion in the desired direction upon a suitable actuation. The first type of frames have been provided with an ability to pivot. The pivots being vertical axillar elements. The arrangement of the two types of frames with pivoted vertical axis provides a plurality of assemblies or shelves mounted on respective door and coplanar portion. The shelves are displaced angularly and laterally owing to the actuating mechanism of the door. The assemblies or shelves are interconnected using coupling elements, horizontal arms and a multiplicity of pivot points arranged at pre-determined distances.

Abstract: A method includes receiving first data at a controller of an ADAS via a first virtual channel of a camera serial interface 2 (CSI-2) data interface. The method also includes receiving second data at the controller of the ADAS via a second virtual channel of the CSI-2 data interface. The method includes storing the first data at a first address in a memory, the first address specified by the first virtual channel. The method also includes storing the second data at a second address of a control register, the control register specified by the second data. The method includes performing a test using the first data and the second data.

Abstract: A computer-implemented method for efficiently dispatching one or more autonomous vehicles to deliver medical supplies to a destination. The method determines a level of emergency and a disease condition at the destination via a user communication interface on the one or more autonomous vehicles. The method prioritizes dispatching the one or more autonomous vehicles based on the level of emergency and the disease condition at the destination. The method optimizes a route of the one or more autonomous vehicles to the destination. The method further integrates a plurality of available data sources across multiple locations, compares these data sources, and builds deep learning (DL) forecasting models to predict several different medicines required, corresponding to a distribution of the disease condition, across the multiple locations.

Abstract: A non-transitory computer-readable medium stores instructions executable by a processor to process data from a radar circuit having multiple antennas.

Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

Abstract: Systems and methods for visualization monitoring data from a cloud-based system include obtaining monitoring data from a cloud-based system, wherein the monitoring data is based on transactions associated with a plurality of users of a cloud environment; providing a Graphical User Interface (GUI) comprising a plurality of columns wherein each column comprises a plurality of filter cards; obtaining a plurality of filter card selections as inputs from the GUI; and displaying log data based on the plurality of filter card selections. The monitoring data can be for one or more of cloud security service transactions, application access via a Zero Trust Network Access (ZTNA) service, user experience metrics, and files accessed via the cloud environment.

Abstract: A cascaded radar system is provided that includes a first radar system-on-a-chip (SOC) operable to perform an initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels of the radar SOC, a second radar SOC operable to perform the initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels in the radar SOC, and a processing unit coupled to the first radar SOC and the second radar SOC to receive results of the initial portion of signal processing from each radar SOC, the processing unit operable to perform a remaining portion of the signal processing for object detection using these results.

Abstract: A non-transitory computer-readable medium stores instructions executable by a processor to process data from a radar circuit having multiple antennas.

Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

Abstract: A non-transitory computer-readable medium stores instructions that cause processors to obtain an N×M range matrix comprising radar data indexed by velocity and antenna and an M×S steering matrix comprising expected phases indexed by antenna and hypothesis angle. For each unique X×Y range slice corresponding to a particular set of X velocities, processors store the particular range slice in a first buffer. For each unique Y×Z steering slice corresponding to a particular set of Y antenna, processors store the particular steering slice in a second buffer. The processors perform beamforming operations on the range, steering, and intermediate slices, storing the result in a third buffer as the intermediate slice. After each steering and range slice for the particular set of X velocities has been iterated through, the processors store the intermediate slice as a beamforming slice for the particular set of X velocities and the hypothesis angles.

Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

Abstract: A computer system includes memory hardware configured to store structured microservice configuration data having multiple microservice entries each associated with one of multiple microservice applications of a request processing architecture. The system includes processor hardware configured to access structured microservice configuration data to identify the microservice applications of the request processing architecture, subscribing to messages transmitted by the identified microservice applications for event monitoring, and receiving multiple messages transmitted by the identified microservice applications.

Abstract: Methods, apparatus, and systems to replace values in a device are disclosed. An example apparatus includes a processor and a replacement generator coupled to the processor and configured to detect an access, by the processor, of a first instruction at a first address in a first memory, in response to the detected access, compare the first address to a set of trigger instruction address records in a second memory, wherein the set of trigger instruction address records includes a first trigger instruction address record that is associated with a first replacement address record and a first replacement value record, and based on the first address corresponding to the first trigger instruction address record, replace a first value at a second address in a third memory specified by the first replacement address record with a second value specified by the first replacement value record.

Abstract: A personal navigation device includes a correlator for processing GNSS signals from a constellation of satellites A signal is received from a navigation beacon containing a repeating code word, in which the code word includes a number N of samples corresponding to N phases, and in which reception of each code word occurs within a defined time period T. The sequence of N code samples is correlated with a known code word to determine a maximum value of correlation for a particular phase of the received signal. The correlation is performed using a correlator of size M, in which M is less than N, such that N/M=P complete correlations for a partial code phase are performed such that each correlation of a partial code phase is performed within a time period of approximately T/P. All P correlations of partial code phases are completed within time T.

Abstract: A method for synchronizing devices in a vehicle may make use of the Controller Area Network (CAN) communication bus. A bus interface of each of two or more devices coupled to the bus may be configured to accept a same message broadcast via the communication bus, in which the message has a specific message identification (ID) header. A message may be received from the communication bus that has the specific message ID simultaneously by each of the two or more devices. Operation of the two or more devices may be synchronized by triggering a task on each of the two or more devices in response to receiving the message having the specific message ID.

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.