Patents by Inventor Jasbir Singh

Jasbir Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10981933
    Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: April 20, 2021
    Assignee: BIOMARIN PHARMACEUTICAL INC.
    Inventors: Vincent Jacques, James R. Rusche, Norton P. Peet, Jasbir Singh
  • Publication number: 20210018632
    Abstract: A personal navigation device includes a correlator for processing GNSS signals from a constellation of satellites A signal is received from a navigation beacon containing a repeating code word, in which the code word includes a number N of samples corresponding to N phases, and in which reception of each code word occurs within a defined time period T. The sequence of N code samples is correlated with a known code word to determine a maximum value of correlation for a particular phase of the received signal. The correlation is performed using a correlator of size M, in which M is less than N, such that N/M=P complete correlations for a partial code phase are performed such that each correlation of a partial code phase is performed within a time period of approximately T/P. All P correlations of partial code phases are completed within time T.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 21, 2021
    Inventors: Jasbir Singh Nayyar, Sreenath Narayanan Potty, Sunil Chomal
  • Publication number: 20200388346
    Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.
    Type: Application
    Filed: August 26, 2020
    Publication date: December 10, 2020
    Inventors: Prakash NARAYANAN, Nikita NARESH, Prathyusha Teja INUGANTI, Rakesh Channabasappa YARADUYATHINAHALLI, Aravinda ACHARYA, Jasbir SINGH, Naveen Ambalametil NARAYANAN
  • Patent number: 10838391
    Abstract: Disclosed is a system for swapping springs present in a product. A data receiving module receives metadata associated to a spring. The metadata comprises a pitch, vector coordinates and alike. A comparison module compares the pitch associated to the spring with a predefined threshold value thereby categorizing each spring into one of a category including a utilized spring category and an underutilized spring category. A determination module determines an underutilized spring, amongst the underutilized spring category, based on at least one of the vector coordinates and the pitch, when the spring is categorized in the utilized spring category. Subsequent to determining the underutilized spring, the swapping module swaps the spring with the underutilized spring by using a control mechanism.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: November 17, 2020
    Inventors: Jasbir Singh Dhaliwal, Ashita Dhir, Mahesh Kaladaikurchi Subramaniam, Venkat Sharan Tirumalai Vinjumur
  • Patent number: 10818374
    Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: October 27, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prakash Narayanan, Nikita Naresh, Prathyusha Teja Inuganti, Rakesh Channabasappa Yaraduyathinahalli, Aravinda Acharya, Jasbir Singh, Naveen Ambalametil Narayanan
  • Patent number: 10816673
    Abstract: A personal navigation device includes a correlator for processing GNSS signals from a constellation of satellites A signal is received from a navigation beacon containing a repeating code word, in which the code word includes a number N of samples corresponding to N phases, and in which reception of each code word occurs within a defined time period T. The sequence of N code samples is correlated with a known code word to determine a maximum value of correlation for a particular phase of the received signal. The correlation is performed using a correlator of size M, in which M is less than N, such that N/M=P complete correlations for a partial code phase are performed such that each correlation of a partial code phase is performed within a time period of approximately T/P. All P correlations of partial code phases are completed within time T.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: October 27, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Sreenath Narayanan Potty, Sunil Chomal
  • Publication number: 20200233758
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Inventors: JASBIR SINGH NAYYAR, SHASHANK SRINIVASA NUTHAKKI, RAHUL GULATI, ARUN SHRIMALI
  • Publication number: 20200225318
    Abstract: A radar system is provided that includes a receive channel including a complex baseband and a processor coupled to the receive channel to receive a first plurality of digital intermediate frequency (IF) samples from an in-band (I) channel of the complex baseband and a corresponding second plurality of digital IF samples from a quadrature (Q) channel of the complex baseband, wherein the processor is configured to execute instructions to compute at least one failure metric based on the first plurality of digital IF samples and the second plurality of digital IF samples.
    Type: Application
    Filed: March 31, 2020
    Publication date: July 16, 2020
    Inventors: Karthik Ramasubramanian, Karthik Subburaj, Jasbir Singh Nayyar
  • Publication number: 20200225315
    Abstract: A cascaded radar system is provided that includes a first radar system-on-a-chip (SOC) operable to perform an initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels of the radar SOC, a second radar SOC operable to perform the initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels in the radar SOC, and a processing unit coupled to the first radar SOC and the second radar SOC to receive results of the initial portion of signal processing from each radar SOC, the processing unit operable to perform a remaining portion of the signal processing for object detection using these results.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 16, 2020
    Inventors: Jasbir Singh Nayyar, Brian Paul Ginsburg, Sudipto Bose, Murtaza Ali
  • Patent number: 10712562
    Abstract: Disclosed is a method and system for enabling immersive viewing of a multimedia. The method may comprise receiving multimedia from one or more source devices, a user data associated with a user wearing an eyewear, a display device data associated with a display device, and an alignment data. The eyewear may comprise a regular glass and a smart glass, and the display device data may comprise dimensions of the display device. The method may further comprise dividing the multimedia in to a primary multimedia and a secondary multimedia based on one or more of the user data, the display device data, and the alignment data. The method may furthermore comprise transmitting the primary multimedia to the display device for display on the display device and transmitting the secondary multimedia to the eyewear for display on the smart glass, thereby enabling immersive viewing of a multimedia.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 14, 2020
    Assignee: HCL Technologies Limited
    Inventors: Jasbir Singh Dhaliwal, Sankar Uma Tammana
  • Publication number: 20200199757
    Abstract: A method for applying an anti-corrosion coating to a substrate includes: applying an anti-corrosion composition; and applying a dye which exhibits fluorescence when exposed to ultraviolet radiation.
    Type: Application
    Filed: November 11, 2019
    Publication date: June 25, 2020
    Inventor: Jasbir Singh AUJLA
  • Patent number: 10659078
    Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 19, 2020
    Assignee: TEXAS INTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Brian Ginsburg, Karthik Subburaj
  • Publication number: 20200148704
    Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).
    Type: Application
    Filed: November 8, 2019
    Publication date: May 14, 2020
    Inventors: Vincent Jacques, James R. Rusche, Norton P. Peet, Jasbir Singh
  • Patent number: 10649865
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: May 12, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Shashank Srinivasa Nuthakki, Rahul Gulati, Arun Shrimali
  • Patent number: 10641866
    Abstract: A radar system is provided that includes a receive channel including a complex baseband and a processor coupled to the receive channel to receive a first plurality of digital intermediate frequency (IF) samples from an in-band (I) channel of the complex baseband and a corresponding second plurality of digital IF samples from a quadrature (Q) channel of the complex baseband, wherein the processor is configured to execute instructions to compute at least one failure metric based on the first plurality of digital IF samples and the second plurality of digital IF samples.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Karthik Ramasubramanian, Karthik Subburaj, Jasbir Singh Nayyar
  • Publication number: 20200135290
    Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.
    Type: Application
    Filed: February 8, 2019
    Publication date: April 30, 2020
    Inventors: Prakash NARAYANAN, Nikita NARESH, Prathyusha Teja INUGANTI, Rakesh Channabasappa YARADUYATHINAHALLI, Aravinda ACHARYA, Jasbir SINGH, Naveen Ambalametil NARAYANAN
  • Patent number: 10627480
    Abstract: A cascaded radar system is provided that includes a first radar system-on-a-chip (SOC) operable to perform an initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels of the radar SOC, a second radar SOC operable to perform the initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels in the radar SOC, and a processing unit coupled to the first radar SOC and the second radar SOC to receive results of the initial portion of signal processing from each radar SOC, the processing unit operable to perform a remaining portion of the signal processing for object detection using these results.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Brian Paul Ginsburg, Sudipto Bose, Murtaza Ali
  • Publication number: 20200010504
    Abstract: The present technology relates to compounds, kits, compositions, and methods useful for the treatment of numerous pathologies including dementia, Alzheimer's disease, Parkinson's disease, amyotrophic lateral sclerosis, and other neurodegenerative diseases, spinal cord injury, traumatic brain injury, diabetes and metabolic syndrome, defective wound healing, and/or sensorineural hearing and vision loss.
    Type: Application
    Filed: June 1, 2017
    Publication date: January 9, 2020
    Inventors: Leen H. KAWAS, Jasbir SINGH, Lansing Joseph STEWART, William R. BAKER
  • Patent number: 10526346
    Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: January 7, 2020
    Assignee: BIOMARIN PHARMACEUTICAL INC.
    Inventors: Vincent Jacques, James R. Rusche, Norton P. Peet, Jasbir Singh
  • Publication number: 20190233439
    Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).
    Type: Application
    Filed: March 12, 2019
    Publication date: August 1, 2019
    Inventors: Vincent Jacques, James R. Rusche, Norton P. Peet, Jasbir Singh