Patents by Inventor Jasbir Singh

Jasbir Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10280182
    Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 7, 2019
    Assignee: BIOMARIN PHARMACEUTICAL INC.
    Inventors: Vincent Jacques, James R. Rusche, Norton P. Peet, Jasbir Singh
  • Publication number: 20190101887
    Abstract: Disclosed is a system for swapping springs present in a product. A data receiving module receives metadata associated to a spring. The metadata comprises a pitch, vector coordinates and alike. A comparison module compares the pitch associated to the spring with a predefined threshold value thereby categorizing each spring into one of a category including a utilized spring category and an underutilized spring category. A determination module determines an underutilized spring, amongst the underutilized spring category, based on at least one of the vector coordinates and the pitch, when the spring is categorized in the utilized spring category. Subsequent to determining the underutilized spring, the swapping module swaps the spring with the underutilized spring by using a control mechanism.
    Type: Application
    Filed: October 2, 2018
    Publication date: April 4, 2019
    Inventors: Jasbir Singh DHALIWAL, Ashita DHIR, Mahesh Kaladaikurchi SUBRAMANIAM, Venkat Sharan TIRUMALAI VINJUMUR
  • Publication number: 20190097651
    Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 28, 2019
    Inventors: Jasbir Singh Nayyar, Brian Ginsburg, KARTHIK SUBBURAJ
  • Publication number: 20190084973
    Abstract: Premature termination codon readthrough prodrug compounds, compositions thereof, and methods of making and using the same are provided. In certain embodiments, the compounds are of Formula Ia or a pharmaceutically acceptable salt, solvate, polymorph, hydrate, ester, isomer, stereoisomer, or tautomer thereof, wherein R, A and W are as described herein.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 21, 2019
    Inventors: Carmen Bertoni, Jasbir Singh
  • Publication number: 20180370987
    Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).
    Type: Application
    Filed: July 26, 2018
    Publication date: December 27, 2018
    Inventors: Vincent Jacques, James R. Rusche, Norton P. Peet, Jasbir Singh
  • Patent number: 10142095
    Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: November 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Brian Ginsburg, Karthik Subburaj
  • Publication number: 20180327423
    Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Inventors: Vincent Jacques, James R. Rusche, Norton P. Peet, Jasbir Singh
  • Publication number: 20180285218
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Application
    Filed: May 29, 2018
    Publication date: October 4, 2018
    Inventors: Jasbir Singh Nayyar, Shashank Srinivasa Nuthakki, Rahul Gulati, Arun Shrimali
  • Patent number: 10077260
    Abstract: Premature termination codon readthrough prodrug compounds, compositions thereof, and methods of making and using the same are provided. In certain embodiments, the compounds are of Formula Ia or a pharmaceutically acceptable salt, solvate, polymorph, hydrate, ester, isomer, stereoisomer, or tautomer thereof, wherein R, A and W are as described herein.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: September 18, 2018
    Assignee: The Regents of the University of California
    Inventors: Carmen Bertoni, Jasbir Singh
  • Patent number: 10078139
    Abstract: A helmet for tracking compliance information associated with a rider is disclosed. The helmet comprising a Global Positioning System (GPS) configured to trace a complete path covered by the rider. Further, the helmet comprises a set of biometric sensor configured to capture biometric sample of the rider at regular intervals, when the rider is in motion. Furthermore, the helmet comprises a data processing platform. The data processing platform maintains a database configured to store a profile data of the rider such as biometric information and identity profile of the rider. The data processing platform enables a biometric data analysis module configured to classify the complete path into a compliant path and a non-compliant path by analyzing the biometric information and biometric samples captured from the rider. Further, the data processing platform enables a data transmission module to transmit the compliant path and the non compliant path to a remote server.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: September 18, 2018
    Assignee: HCL TECHNOLOGIES LTD.
    Inventor: Jasbir Singh Dhaliwal
  • Patent number: 10059723
    Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: August 28, 2018
    Assignee: BIOMARIN PHARMACEUTICAL INC.
    Inventors: Vincent Jacques, James R. Rusche, Norton P. Peet, Jasbir Singh
  • Publication number: 20180208606
    Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).
    Type: Application
    Filed: January 3, 2018
    Publication date: July 26, 2018
    Inventors: Vincent Jacques, James R. Rusche, Norton P. Peet, Jasbir Singh
  • Publication number: 20180203096
    Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.
    Type: Application
    Filed: March 15, 2018
    Publication date: July 19, 2018
    Inventors: Tom Altus, Jasbir Singh Nayyar, Karthik Ramasubramanian, Brian Paul Ginsburg
  • Patent number: 10002056
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: June 19, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Shashank Srinivasa Nuthakki, Rahul Gulati, Arun Shrimali
  • Publication number: 20180159647
    Abstract: A method for synchronizing devices in a vehicle may make use of the Controller Area Network (CAN) communication bus. A bus interface of each of two or more devices coupled to the bus may be configured to accept a same message broadcast via the communication bus, in which the message has a specific message identification (ID) header. A message may be received from the communication bus that has the specific message ID simultaneously by each of the two or more devices. Operation of the two or more devices may be synchronized by triggering a task on each of the two or more devices in response to receiving the message having the specific message ID.
    Type: Application
    Filed: December 2, 2016
    Publication date: June 7, 2018
    Inventors: Jasbir Singh Nayyar, Brian Paul Ginsburg
  • Publication number: 20180115409
    Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.
    Type: Application
    Filed: October 26, 2016
    Publication date: April 26, 2018
    Inventors: JASBIR SINGH NAYYAR, BRIAN GINSBURG, KARTHIK SUBBURAJ
  • Patent number: 9920571
    Abstract: An integrated controller for an operator unit for powering an overhead garage roller door or roller shutter is described. The operator unit comprises a motor, an output drive assembly, a timing assembly unit, and a clutch assembly for providing selective engagement between motor powered operation and manual operation (provided by a chain rotating a chain wheel). The motor is arranged to drive a shaft which, in turn, provides drive to the roller door or shutter assembly (not shown), which includes an axle around which the roller door or shutter is wound. The integrated controller comprises an inverter for receiving a single phase power supply and supplying three phase power to drive the motor; and a drive controller in operable association with the inverter for providing active management of the operation of the motor.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: March 20, 2018
    Assignee: Automatic Technology (Australia) Pty. Ltd.
    Inventors: Travis William Smith, Geoff Baker, Nikolai Klepikov, Jasbir Singh, Ray Hawkins
  • Patent number: 9921295
    Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: March 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tom Altus, Jasbir Singh Nayyar, Karthik Ramasubramanian, Brian Paul Ginsburg
  • Patent number: 9908899
    Abstract: The compounds provided herein are phenyl analine amides and are useful for inhibiting histone deacteylase (“HDAC”) enzymes, such as HDAC1, HDAC2, and HDAC3.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: March 6, 2018
    Assignee: BIOMARIN PHARMACEUTICAL INC.
    Inventors: Vincent Jacques, James R. Rusche, Norton P. Peet, Jasbir Singh
  • Publication number: 20180038943
    Abstract: A radar system is provided that includes a receive channel including a complex baseband and a processor coupled to the receive channel to receive a first plurality of digital intermediate frequency (IF) samples from an in-band (I) channel of the complex baseband and a corresponding second plurality of digital IF samples from a quadrature (Q) channel of the complex baseband, wherein the processor is configured to execute instructions to compute at least one failure metric based on the first plurality of digital IF samples and the second plurality of digital IF samples.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Karthik Ramasubramanian, Karthik Subburaj, Jasbir Singh Nayyar