Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

Abstract: A method for synchronizing devices in a vehicle may make use of the Controller Area Network (CAN) communication bus. A bus interface of each of two or more devices coupled to the bus may be configured to accept a same message broadcast via the communication bus, in which the message has a specific message identification (ID) header. A message may be received from the communication bus that has the specific message ID simultaneously by each of the two or more devices. Operation of the two or more devices may be synchronized by triggering a task on each of the two or more devices in response to receiving the message having the specific message ID.

Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.

Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

Abstract: An integrated controller for an operator unit for powering an overhead garage roller door or roller shutter is described. The operator unit comprises a motor, an output drive assembly, a timing assembly unit, and a clutch assembly for providing selective engagement between motor powered operation and manual operation (provided by a chain rotating a chain wheel). The motor is arranged to drive a shaft which, in turn, provides drive to the roller door or shutter assembly (not shown), which includes an axle around which the roller door or shutter is wound. The integrated controller comprises an inverter for receiving a single phase power supply and supplying three phase power to drive the motor; and a drive controller in operable association with the inverter for providing active management of the operation of the motor.

Abstract: The compounds provided herein are phenyl analine amides and are useful for inhibiting histone deacteylase (“HDAC”) enzymes, such as HDAC1, HDAC2, and HDAC3.

Abstract: A radar system is provided that includes a receive channel including a complex baseband and a processor coupled to the receive channel to receive a first plurality of digital intermediate frequency (IF) samples from an in-band (I) channel of the complex baseband and a corresponding second plurality of digital IF samples from a quadrature (Q) channel of the complex baseband, wherein the processor is configured to execute instructions to compute at least one failure metric based on the first plurality of digital IF samples and the second plurality of digital IF samples.

Abstract: A method of radar signal processing includes providing an analog front end (AFE) including an amplifier coupled between an antenna and an ADC in a receive path, where an ADC output is coupled to an input of an elastic ADC buffer (elastic buffer) including a divided memory with for writing samples from the ADC (samples) while reading earlier written samples to a first signal processor by a high speed interface. A transmit path includes at least one power amplifier provided by the AFE coupled to drive an antenna. A Greatest Common Divisor (GCD) is determined across all chirps in a radar frame programmed to be used. For each frame a sample size for the elastic buffer is dynamically controlled constant to be equal to the GCD for reading samples from one memory block and writing samples to another memory block throughout all chirps in the frame.

Abstract: Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search.

Abstract: Disclosed is a method and system for enabling immersive viewing of a multimedia. The method may comprise receiving multimedia from one or more source devices, a user data associated with a user wearing an eyewear, a display device data associated with a display device, and an alignment data. The eyewear may comprise a regular glass and a smart glass, and the display device data may comprise dimensions of the display device. The method may further comprise dividing the multimedia in to a primary multimedia and a secondary multimedia based on one or more of the user data, the display device data, and the alignment data. The method may furthermore comprise transmitting the primary multimedia to the display device for display on the display device and transmitting the secondary multimedia to the eyewear for display on the smart glass, thereby enabling immersive viewing of a multimedia.

Abstract: A method of radar signal processing includes providing an analog front end (AFE) including an amplifier coupled between an antenna and an ADC in a receive path, where an ADC output is coupled to an input of an elastic ADC buffer (elastic buffer) including a divided memory with for writing samples from the ADC (samples) while reading earlier written samples to a first signal processor by a high speed interface. A transmit path includes at least one power amplifier provided by the AFE coupled to drive an antenna. A Greatest Common Divisor (GCD) is determined across all chirps in a radar frame programmed to be used. For each frame a sample size for the elastic buffer is dynamically controlled constant to be equal to the GCD for reading samples from one memory block and writing samples to another memory block throughout all chirps in the frame.

Abstract: A method of radar signal processing includes providing an analog front end (AFE) including an amplifier coupled between an antenna and an ADC in a receive path, where an ADC output is coupled to an input of an elastic ADC buffer (elastic buffer) including a divided memory with for writing samples from the ADC (samples) while reading earlier written samples to a first signal processor by a high speed interface. A transmit path includes at least one power amplifier provided by the AFE coupled to drive an antenna. A Greatest Common Divisor (GCD) is determined across all chirps in a radar frame programmed to be used. For each frame a sample size for the elastic buffer is dynamically controlled constant to be equal to the GCD for reading samples from one memory block and writing samples to another memory block throughout all chirps in the frame.

Abstract: A personal navigation device includes a correlator for processing GNNS signals from a constellation of satellites A signal is received from a navigation beacon containing a repeating code word, in which the code word includes a number N of samples corresponding to N phases, and in which reception of each code word occurs within a defined time period T. The sequence of N code samples is correlated with a known code word to determine a maximum value of correlation for a particular phase of the received signal. The correlation is performed using a correlator of size M, in which M is less than N, such that N/M=P complete correlations for a partial code phase are performed such that each correlation of a partial code phase is performed within a time period of approximately T/P. All P correlations of partial code phases are completed within time T.

Abstract: A GNSS receiver configured to detect a presence of at least one GNSS satellite signal in a received signal is provided. The GNSS receiver includes a buffer loaded with sample sets corresponding to the received signal and a Doppler derotation block configured to perform a Doppler derotation corresponding to at least one Doppler frequency on a sample set received from the buffer. The GNSS receiver further includes an accumulator block configured to perform a coherent accumulation of a plurality of sample sets upon or subsequent to the Doppler derotation corresponding to a Doppler frequency, and, a first memory configured to store the results of the coherent accumulation. A register array is configured to be loaded with the results stored in the first memory and a correlator engine is configured to generate correlation results by correlating the results in the register array with a plurality of code phases of GNSS satellites.

Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).

Abstract: This invention relates to generally inhibiting histone deacetylase (“HDAC”) enzymes (e.g., HDAC1, HDAC2, and HDAC3).

Abstract: Disclosed is an electronic wallet that may comprise a biometric authentication module for authenticating an owner of the electronic wallet. The owner may be authenticated by verifying authentication credentials received from the owner. The electronic wallet further comprises a scanner configured to scan one or more currency notes inserted or withdrawn for determine an amount of the one or more currency notes present in the electronic wallet. The electronic wallet further comprises a wireless communication means for establishing a communication channel between the electronic wallet and a communication device. The electronic wallet further comprises a demagnetization means for demagnetizing a snip of a financial instrument present in the electronic wallet based upon occurrence of at least one of the predefined events thereby rendering the financial instrument useless in order to avoid misuse of the electronic wallet.

Abstract: This invention relates to generally inhibiting histone deacetylase (HDAC) enzymes (e.g., HDAC1, HDAC2, and HDAC3).

Abstract: The present disclosure relates to system(s) and method(s) for systems and methods for controlling resources in an Internet of Things (IoT) network. The system comprises a processor and a memory coupled to the processor, wherein the processor is configured for detecting presence of a user in a vicinity of an Internet of Things (IoT) network. Further, the processor is configured for receiving the biometric authentication information and the profile identifier from the wearable device. The biometric authentication information is generated by the wearable device based on comparison of a biometric sample captured from the user with a golden copy of the biometric sample. Furthermore, the processor is configured for identifying a user profile associated with the user based on the biometric authentication information and the profile identifier. Once the user profile is identified, in the next step, the processor is configured for calibrating the one or more resources in the IoT network based on the user profile.