Patents by Inventor Jasmin Ajanovic

Jasmin Ajanovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6976115
    Abstract: A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Kenneth Creta, Jasmin Ajanovic, Joseph Bennett
  • Publication number: 20050251611
    Abstract: In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header information. In one such embodiment, the first header may be a header of a first protocol and the second header may be of a different protocol that is used to tunnel the transaction through the coherent system.
    Type: Application
    Filed: April 27, 2004
    Publication date: November 10, 2005
    Inventors: Kenneth Creta, Robert Blankenship, Sridhar Muthrasanallur, Jasmin Ajanovic
  • Publication number: 20050235067
    Abstract: Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 20, 2005
    Inventors: Kenneth Creta, Aaron Spink, Lance Hacking, Sridhar Muthrasanallur, Jasmin Ajanovic
  • Publication number: 20040128449
    Abstract: To reduce prefetch overshoot when prefetching partial data sets along the path from input-output bus to system memory, a prefetch field is used to communicate the amount of data that a prefetching entity upstream may prefetch. Utilizing a prefetch field in such a manner reduces the fetching of unneeded data past the end of the requested data, resulting in overall increased system performance.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Inventors: Randy B. Osborne, Kenneth C. Creta, Joseph A. Bennett, Jasmin Ajanovic
  • Patent number: 6718512
    Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: April 6, 2004
    Assignee: Intel Corporation
    Inventors: Randy B. Osborne, Jasmin Ajanovic
  • Publication number: 20040044820
    Abstract: A point-to-point interconnection and communication architecture, protocol and related methods is presented.
    Type: Application
    Filed: September 3, 2003
    Publication date: March 4, 2004
    Inventors: Jasmin Ajanovic, David Harriman
  • Patent number: 6691192
    Abstract: A point-to-point interconnection and communication architecture, protocol and related methods is presented.
    Type: Grant
    Filed: September 30, 2001
    Date of Patent: February 10, 2004
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman
  • Patent number: 6636912
    Abstract: According to one embodiment, a computer comprises a central processing unit (CPU), a first hub agent, a first hub interface coupled to the first hub agent, and a second hub agent coupled to the first hub interface. The first and second hub agents operate at a first data clocking rate determined by exchanging data clocking rate capabilities.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: October 21, 2003
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David J. Harriman, David I. Poisner
  • Publication number: 20030188072
    Abstract: A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 2, 2003
    Inventors: Kenneth Creta, Jasmin Ajanovic, Joseph Bennett
  • Publication number: 20030182591
    Abstract: According to one embodiment, a computer comprises a central processing unit (CPU), a first hub agent, a first hub interface coupled to the first hub agent, and a second hub agent coupled to the first hub interface. The first and second hub agents operate at a first data clocking rate determined by exchanging data clocking rate capabilities.
    Type: Application
    Filed: October 7, 1999
    Publication date: September 25, 2003
    Inventors: JASMIN AJANOVIC, DAVID J. HARRIMAN, DAVID I. POISNER
  • Publication number: 20030174716
    Abstract: A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found then the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.
    Type: Application
    Filed: December 28, 2001
    Publication date: September 18, 2003
    Inventors: David M. Lee, Kenneth C. Creta, Jasmin Ajanovic, Gary Solomon, David Harriman
  • Patent number: 6615306
    Abstract: A method and apparatus for reducing flow control and minimizing interface acquisition latency in a hub interface is a method of transferring data between a control hub coupled to a hub interface which is coupled to an input-output hub including the following: Transferring the data in packets. Prioritizing isochronous transfers over asynchronous transfers. Limiting asynchronous transfers to 32 bytes per packet when an agent requests the hub interface, and limiting asynchronous transfers to 64 bytes per packet when no requests for the hub interface are recognized.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: September 2, 2003
    Assignee: Intel Corporation
    Inventor: Jasmin Ajanovic
  • Publication number: 20030158992
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: August 23, 2002
    Publication date: August 21, 2003
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David M. Lee
  • Publication number: 20030145134
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: August 23, 2002
    Publication date: July 31, 2003
    Inventors: Eric R. Wehage, Jasmin Ajanovic, David Harriman, David M. Lee, Blaise Fanning, Buck Gremel, Ken Creta, Wayne Moore
  • Publication number: 20030131179
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: August 22, 2002
    Publication date: July 10, 2003
    Inventors: Jasmin Ajanovic, Hong Jiang, David Harriman
  • Publication number: 20030126552
    Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.
    Type: Application
    Filed: February 6, 2003
    Publication date: July 3, 2003
    Inventors: Randy B. Osborne, Jasmin Ajanovic
  • Publication number: 20030126535
    Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet for a request transaction to a receiving device. The receiving device checks for error conditions. If an error condition exists and if the packet for the request transaction indicates that a completion is not expected by the transmitting device, an error message is delivered by the receiving device to the transmitting device.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 3, 2003
    Inventors: Gary Solomon, David Harriman, Jasmin Ajanovic
  • Publication number: 20030126274
    Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet that includes a format field to partially specify the packet header format and a type field to specify a transaction type. The format field and the type field together specify the packet header format and the format field indicates the size of the packet header.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 3, 2003
    Inventors: David Harriman, Jasmin Ajanovic
  • Patent number: 6587988
    Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: July 1, 2003
    Assignee: Intel Corporation
    Inventors: Randy B. Osborne, Jasmin Ajanovic
  • Publication number: 20030115380
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: August 23, 2002
    Publication date: June 19, 2003
    Inventors: Jasmin Ajanovic, David Harriman, Randolph L. Campbell, Jose A. Vargas, Clifford D. Hall, Prashant Sethi, Steve Pawlowski