Abstract: A point-to-point interconnection and communication architecture, protocol and related methods is presented.

Abstract: A point-to-point interconnection and communication architecture, protocol and related methods is presented.

Abstract: An interface to transfer data between a memory control hub and an input/output control hub of a chipset within a computer system. One embodiment of the interface includes a bi-directional data signal path and a pair of source synchronous strobe signals. The data signal path transmits data in packets via split transactions. In addition, the packets include a request packet and a completion packet, if necessary. Furthermore, in one embodiment, the request packets include a transaction descriptor.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: A configuration access request packet is transmitted from a first hub agent onto a hub interface. The configuration access request packet comprises an address formatted in accordance with a peripheral component interconnect (PCI) specification. The configuration access request packet is received from the hub interface by a second hub agent.

Abstract: A first control hub component, within a computer system, having a first logic to synchronize an internal clock generator of the first control hub with an external clock generator in response to the external clock generator transitioning to a high power state. In response to the internal clock generator being synchronized with the external clock generator, the first logic initiates the first control hub to transmit a request packet to a second control hub via an interface. The first logic monitors the interface for receipt of a completion packet in reply to the request packet, wherein in response to the completion packet the first control hub is operable to continue communication with the second hub via the interface.

Abstract: According to one embodiment, a method comprises receiving a first set of status signals at an input/output control hub (ICH), transmitting a first set of virtual signals corresponding to the first set of status signals to a memory control hub (MCH) via a hub interface. Subsequently, the first set of virtual signals are transmitted to a central processing unit (CPU). The first set of status signals corresponding to one or more legacy operations in a computer system.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: According to one embodiment, a computer system includes a first hub agent and a hub interface coupled to the first hub agent. The first hub agent is adaptable to sample the hub interface in order to detect the presence of a second hub agent upon initiation of the computer system. In a further embodiment, the first hub agent comprises a presence detect module and control logic coupled to the presence detect module. The control logic responds to a central processing unit (CPU) poll request if the second hub agent is detected and does not respond to the CPU if the first device is not detected.

Abstract: A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.

Abstract: A memory controller for use with a memory sub-system selected to have one of multiple memory organizations. The memory controller includes output drivers connected to output pins, the output drivers being programmable to have one of multiple output characteristics. The memory controller also includes a configuration register storing a programmable value that determines the output characteristic.

Abstract: One embodiment of an apparatus for communicating routing and attribute information for a transaction between hubs in a computer system is disclosed. The apparatus includes a data path input/output unit to output a packet header for a transaction. The packet header includes a transaction descriptor routing field to identify an initiating agent that initiated the transaction. The transaction descriptor routing field includes a hub identification portion and a pipe identification portion. The hub identification portion identifies a hub that contains the initiating agent. The pipe identification portion further identifies the initiating agent within the identified hub if the transaction has no ordering requirements with respect to a second agent in the identified hub.

Abstract: A memory controller for a computer system includes a first memory address bus and a second memory, address bus. The memory controller further includes circuitry that toggles one of the first and second memory address buses at a time. Because only one memory address bus is toggled at once, the first and second memory address buses can share power and ground pins, thereby reducing the number of power and ground pins on the memory controller.

Abstract: An apparatus for reusing arbitration signals to frame data transfers between hub agents is disclosed. The apparatus includes an arbitration signal output circuit to output a first request signal to indicate a data transfer. The apparatus further includes a data path input/output unit to output data to a data path during a period indicated by the arbitration signal.

Abstract: An apparatus for arbitrating ownership of an interface between two hub agents is described. The apparatus includes a data path input/output unit to communicate with a data path and an arbitration circuit. The arbitration unit includes a least recently serviced status tracking circuit to determine which of the data path input/output unit and a device that transmits the second request signal has been granted ownership of the data path least recently, an arbitration signal output circuit to output a first request signal, and an arbitration signal input circuit to receive a second request signal. The arbitration unit grants ownership of the data path to the data path input/output unit when the first request signal is asserted if the second request signal is not asserted.

Abstract: A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.

Abstract: A method and apparatus for throttling high priority memory accesses. An apparatus of the present invention includes an arbiter circuit and a throttling circuit. The arbiter circuit is coupled to receive first and second types of memory access commands and has a preference for the first type of memory access commands. The throttling circuit is coupled to the arbiter and can at least temporarily reduce the preference for the memory access commands of the first type.

Abstract: One embodiment of an apparatus for communicating transaction types between hubs in a computer system includes a data path input/output unit to output a packet header. The packet header includes a request/completion field to indicate whether the packet header is a request packet header or a completion packet header. The packet header also includes a read/write field to indicate whether the packet header is for a read packet or for a write packet. The read/write field further indicates whether a length of data is to follow the packet header. The packet header further includes a data length field to indicate the length of data.

Abstract: An interface to transfer data between a memory controller hub and an input/output (I/O) hub of a chipset within a computer system. One embodiment of the interface includes a bi-directional data signal path and a pair of source synchronous strobe signals. The data signal path transmits data in packets via split transactions. In addition, the packets include a request packet and a completion packet, if necessary. Furthermore, in one embodiment, the request packets include a transaction descriptor.

Abstract: A synchronizing circuit translates signals in a slow clock domain into a fast clock domain. The frequency of the slow clock is a submultiple of the fast clock frequency. A synchronizing pulse signal is developed at the frequency of the slow clock, but is phase synchronized to the fast clock. The synchronizing pulse signal is employed to gate the signal in the slow clock domain so that it is synchronized in the fast clock domain. In a system where the ratio between the fast clock frequency and slow clock frequency is determined by a frequency divisor signal, a snooping circuit is employed to capture the frequency divisor signal to achieve rapid synchronization between the clock domains.