Patents by Inventor Jason Raymond Baumgartner

Jason Raymond Baumgartner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8850372
    Abstract: A computer-implemented method of invariant-guided abstraction includes a processor of a computing device generating one or more invariants corresponding to a design under verification by executing a proof algorithm with an input comprising at least a portion of the design and a specified resource limit. The method further includes deterministically assigning priority information to the one or more invariants generated and to components of the design referenced by said invariants. Finally, the method includes performing invariant-guided localization abstraction on the design model to generate an abstracted design model utilizing the assigned priority information as a localization hint that results in abstractions that are at least one of (a) smaller abstractions and (b) easier to verify abstractions.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Alexander Ivrii, Arie Matsliah, Hari Mony
  • Publication number: 20140115548
    Abstract: A computer-implemented method of invariant-guided abstraction includes a processor of a computing device generating one or more invariants corresponding to a design under verification by executing a proof algorithm with an input comprising at least a portion of the design and a specified resource limit. The method further includes deterministically assigning priority information to the one or more invariants generated and to components of the design referenced by said invariants. Finally, the method includes performing invariant-guided localization abstraction on the design model to generate an abstracted design model utilizing the assigned priority information as a localization hint that results in abstractions that are at least one of (a) smaller abstractions and (b) easier to verify abstractions.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JASON RAYMOND BAUMGARTNER, ALEXANDER IVRII, ARIE MATSLIAH, HARI MONY
  • Patent number: 8627273
    Abstract: Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Shaked Flur, Ziv Nevo, Paul Joseph Roessler
  • Patent number: 7930672
    Abstract: A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
  • Patent number: 7921394
    Abstract: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
  • Patent number: 7917874
    Abstract: A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Geert Janssen, Hari Mony, Viresh Paruthi
  • Patent number: 7913218
    Abstract: A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: March 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
  • Patent number: 7913205
    Abstract: A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: March 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Geert Janssen, Hari Mony, Viresh Paruthi
  • Patent number: 7908575
    Abstract: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: March 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
  • Patent number: 7882459
    Abstract: A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
  • Publication number: 20110022373
    Abstract: Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example.
    Type: Application
    Filed: July 22, 2009
    Publication date: January 27, 2011
    Applicant: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Shaked Flur, Ziv Nevo, Paul Joseph Roessler
  • Patent number: 7831937
    Abstract: A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: November 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
  • Patent number: 7823093
    Abstract: A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 26, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
  • Patent number: 7788615
    Abstract: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Hari Mony, Viresh Paruthi, Jiazhao Xu
  • Patent number: 7779378
    Abstract: An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist.
    Type: Grant
    Filed: July 26, 2008
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
  • Patent number: 7765514
    Abstract: A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representation of said relation. A synthesized gate for said gate representing said OR function and synthesis of a set of representations of relations by iterating said building step and said creating step over one or more variables in said representation of said relation is performed to accumulate a synthesized gate set, which synthesized gate set is returned.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: July 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Geert Janssen, Hari Mony, Viresh Paruthi
  • Patent number: 7752583
    Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Christian Jacobi, Viresh Paruthi, Kai Oliver Weber
  • Patent number: 7752593
    Abstract: A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representation of said relation. A synthesized gate for said gate representing said OR function and synthesis of a set of representations of relations by iterating said building step and said creating step over one or more variables in said representation of said relation is performed to accumulate a synthesized gate set, which synthesized gate set is returned.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Geert Janssen, Hari Mony, Viresh Paruthi
  • Patent number: 7689943
    Abstract: A method, system and computer program product for performing parametric reduction of sequential designs is disclosed. The method comprises receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut gates is identified, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is synthesized to form a gate set, and an abstracted design is formed from the gate set. Verification is performed on the abstracted design to generate verification results.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Geert Janssen, Hari Mony, Viresh Paruthi
  • Patent number: 7509605
    Abstract: An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: March 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi