Abstract: An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced.

Abstract: A formal verification method and apparatus allowing a user, via a waveform-based graphical user interface, to modify the waveform displayed by a verification algorithm by highlighting specific values at specific cycles. The user may begin either from scratch or from an existing trace produced by the tool. After running the tool, the resultant waveform represents a trace that the user wishes to extract from the model using the verification tool. The annotations input by the user are translated to “cycle-specific invariants” to force the tool to produce a trace that satisfies the desired annotated waveform and to insure a much faster and more efficient query. The invariants are then passed to a verification algorithm, which outputs a trace satisfying these invariants. The user determines whether the trace is satisfactory and may add additional constraints to the waveform to derive a subsequent trace until the user is satisfied.

Abstract: An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced.

Abstract: An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced.

Abstract: A method for characterizing average performance in a data processing system is provided. This method consists of adding meta-tool level variables to a verification tool. These meta-tool variables keep track, at once, of all concurrent streams of execution that the tool is considering in its reachability analysis. The image of an initial state variable is found and then divided into a frontier of new states and a set of previously reached states. The previously reached states are ignored and the image of the frontier is found. This process continues until the frontier is empty and all possible states have been reached. In one embodiment of the present invention, the probabilities of the paths can be considered by sampling and holding input data using SMV (a model checking tool) variables.

Abstract: A design verification system comprising a set of modular verification engines invoked by a framework that manages the control flow between the engines. The framework receives a verification problem from an application and attempts to solve it by instantiating one or more engine in a customizable sequence or set of sequences. Each verification engine is configured to achieve a specific verification objective and may be coded against a common API to facilitate exchange of information between the engines. The verification engines may include reduction engines, which attempt to simplify a problem by modifying it or decomposing it, and decision engines, which attempt to solve problems that are passed to them. As a verification problem is passed from one engine to the next, the engine may alter the verification problem such that a decision engine at the end of the sequence may receive a verification problem that is simpler to solve than the original problem specified by the system user.

Abstract: A method and system for transmitting video data are disclosed. The method includes receiving a first video image and comparing the first video image to at least one stock image where each of the stock images is associated with a corresponding index value. If a match between at least a portion of the first video image and one of the at least one stock images is detected, the index value corresponding to the matching stock image is transmitted over a transmission medium. In one embodiment, the method further includes receiving the transmitted index value and generating the corresponding stock image from the index value. The method of may further includes comparing the first video image with a set of stock images. If it is determined that the first image does not match to any of the set of stock images, then a new index value is assigned to the first image and the first image is added to the set of stock images.

Abstract: An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced.

Abstract: An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced.

Abstract: An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced.

Abstract: A design verification system comprising a set of modular verification engines invoked by a framework that manages the control flow between the engines. The framework receives a verification problem from an application and attempts to solve it by instantiating one or more engine in a customizable sequence or set of sequences. Each verification engine is configured to achieve a specific verification objective and may be coded against a common API to facilitate exchange of information between the engines. The verification engines may include reduction engines, which attempt to simplify a problem by modifying it or decomposing it, and decision engines, which attempt to solve problems that are passed to them. As a verification problem is passed from one engine to the next, the engine may alter the verification problem such that a decision engine at the end of the sequence may receive a verification problem that is simpler to solve than the original problem specified by the system user.

Abstract: An apparatus performs a process for partitioning a netlist. The process picks a unique color for each clock and traverses the clock tree coloring the latches in support of that clock tree with that color. The process then colors the fanout logic cones for each latch and notes any coloring collisions. In the case of a multicolored gate, the process retimes the network by moving the terminating latch backwards, towards the collision, to enable single coloring of the gate. The process then performs a depth-first search on the fanout logic of each primary input to the first latch encountered or a primary output. If a primary output is encountered, the path is colored with a color representing the free-run domain. Otherwise, the process colors the path with the color of the terminating latch. Next, the process duplicates the fanin cones for remaining multicolored gates so that a copy of the logic can be incorporated with each independent domain.

Abstract: A method of verifying a digital circuit in which state transition information is extracted from the output of a non-formal first verification technique. A formal verification tool is then applied to the extracted state transition information to extend the verification coverage of the digital circuit beyond the coverage that is achieved using the first verification technique. In one embodiment, the method includes the initial step of applying a first verification technique such as a simulation technique to a model of the digital circuit. In the preferred embodiment, the application of the formal verification tool comprises applying a model checker to the extracted state transition data to achieve a formal verification of the state machine represented by the state transition diagram. In one embodiment, the extracted state transition information includes a set of data points each representing a present state, a present input, and a next state.

Abstract: A method and apparatus for dynamically driving events in a simulation of a data processing system are implemented. Events, or system states, are generated by drivers located at predetermined locations within the simulation model under test. These events, which are drawn from a predetermined class of events, termed “effects,” are driven in response to other events observed by monitors disposed within the simulation model in accordance with a predetermined set of “causes,” and a set of “rules” that map causes to effects. The driving of events is mediated by a library process that receives observed events from the monitors, in the form of data structures, stored them in a database, and passes the effects to be driven to the appropriate driver in accordance with the set of rules, also data structures stored in the database, when a cause corresponds to a observed event.

Abstract: A high performance voice transformation apparatus and method is provided in which voice input is transformed into a symbolic representation of phonemes in the voice input. The symbolic representation is used to retrieve output voice segments of a selected target speaker for use in outputting the voice input in a different voice. In addition, voice input characteristics are extracted from the voice input and are then applied to the output voice segments to thereby provide a more realistic human sounding voice output.

Abstract: A method for automatically generating a set of specifications against which a model of the digital circuit can be verified. In one embodiment, the method includes an initial step in which a specification class that corresponds to a type of behavior of the digital circuit is defined. A set of specification formulae that satisfies the defined specification class is then enumerated. Each formula in the set of formulae is then applied to the model of the digital circuit to determine whether the digital circuit satisfies the corresponding formula. The definition of the specification class preferably includes a set of input conditions, a set of output or response conditions, and a temporal component. Preferably, the enumeration of the specification formulae includes all specification formulae that satisfy the specification class. The application of the set of formulae to the model of the digital circuit is preferably achieved with a verification engine such as a model checker.

Abstract: A system and method for compressing data on a computer system is disclosed. The method and system include separating the data into a plurality of segments. The plurality of segments includes a plurality of unique segments. The method and system also include providing a plurality of code words. Each of the plurality of code words corresponds to a unique segment of the plurality of unique segments. The method and system also include providing a representation of the data. The representation includes the plurality of code words for the plurality of segments. The plurality of code words in the representation replaces the plurality of segments. As a result, the data in the representation could be accessed randomly.

Abstract: A method for characterizing average performance in a data processing system is provided. This method consists of adding meta-tool level variables to a verification tool. These meta-tool variables keep track, at once, of all concurrent streams of execution that the tool is considering in its reachability analysis. The image of an initial state variable is found and then divided into a frontier of new states and a set of previously reached states. The previously reached states are ignored and the image of the frontier is found. This process continues until the frontier is empty and all possible states have been reached. In one embodiment of the present invention, the probabilities of the paths can be considered by sampling and holding input data using SMV (a model checking tool) variables.

Abstract: An apparatus performs a process for partitioning a netlist. The process picks a unique color for each clock and traverses the clock tree coloring the latches in support of that clock tree with that color. The process then colors the fanout logic cones for each latch and notes any coloring collisions. In the case of a multicolored gate, the process retimes the network by moving the terminating latch backwards, towards the collision, to enable single coloring of the gate. The process then performs a depth-first search on the fanout logic of each primary input to the first latch encountered or a primary output. If a primary output is encountered, the path is colored with a color representing the free-run domain. Otherwise, the process colors the path with the color of the terminating latch. Next, the process duplicates the fanin cones for remaining multicolored gates so that a copy of the logic can be incorporated with each independent domain.

Abstract: A method of generating a digital circuit model that has fewer latches than the circuit being modeled. Initially, a determination of whether the digital circuit is reducible is made. The digital circuit suitably includes one or more primary inputs, one or more primary outputs, and a plurality of latches comprised of a level one (L1) latch set and a level two (L2) latch set wherein the latch sets may or may not lack one-to-one correspondence. After determining that the digital circuit is reducible, at least one of the latches is replaced with combinational logic thereby reducing the latch count of the digital circuit model.