Abstract: A system and method for compressing state transition data on a computer system is disclosed. The method and system include separating the state transition data into a plurality of segments and separating each of the plurality of segments into a plurality of subsegments. The method and system further include providing a plurality of code words. Each of the plurality of code words corresponds to a unique subsegment of the plurality of unique subsegments. The method and system also include providing a representation of each segment. The representation of each segment includes a portion of the plurality of code words. The portion of the plurality of code words replaces the plurality of subsegments in each of the plurality of segments. Thus, the present invention allows compressed state transition data to be used without full uncompression, allowing a system to be explicitly checked without substantial loss of information and without consuming memory.

Abstract: A method for compressing files utilizing a dictionary within a data-processing system is disclosed. A binary file commonly available to a data-compressing system during compression and to a data-decompressing system during decompression can be served as a dictionary file. A first dictionary array is initially generated utilizing the dictionary file. Each entry within the first dictionary array includes a set of unique bit patterns from the dictionary file. An input file is parsed into multiple blocks, with each block having the same length as each entry within the first dictionary array. The input file is then compared against the first dictionary array, and each entry within the first dictionary array that includes the same bit patterns as a block from the input file is marked accordingly. A second dictionary array that includes all the marked entries from the first dictionary array is subsequently generated, and this second dictionary array is utilized in the compression of the input file.

Abstract: A method and system in an integrated circuit for the detection of defects within integrated circuits and planars are disclosed. Initially, pseudo-random data is generated. Thereafter, the pseudo-random data is transferred to a bus interface unit that determines, based upon the pseudo-random data, a particular transaction that may be injected upon a test unit by the bus interface unit. Expected results of all types of transactions that may be injected upon the test unit are predetermined. The particular transaction is then injected upon the test unit. Such transactions can include transactions such as a bus store or bus load. The results of the particular transaction upon the test unit are then compared with the expected results, wherein a mismatch between the expected results and the results of the particular transaction upon the test unit exposes an error within the test unit, such that a variety of test units may be portably tested for errors without the need for preconfiguring the test units for testing.

Abstract: A method is provided for automatically enhancing verification of a design under test by using model checking on the state transitions captured during simulation. The enhanced verification is due to the fact that even though to all of the individual transitions captured were exercised during simulation, not all possible sequences of those transitions were necessarily exercised during the simulation, and the unexercised sequences may hide "bugs". The non-deterministic and exhaustive nature of the model checker ensures that all possible sequences comprising the captured state transitions are exercised. The methodology consists of utilizing the state transitions, and the inputs causing those state transitions as observed during simulation, to define legitimate input values that can be applied, nondeterministically and exhaustively, by the model checker to the design under test.