Abstract: Methods and apparatus to install voice over Internet Protocol (VoIP) devices are disclosed. An example method comprises receiving a device identifier and an authentication credential from a voice over Internet protocol (VoIP) device, and provisioning the device identifier to a subscriber account based on the authentication credential.

Abstract: A process for manufacturing an integrated circuit using shallow trench isolation (STI) includes a 2-step nitride removal process which, when combined with a nitride pull-back step provides, in a floating gate memory integrated circuit, a high coupling ratio and a reduction in thinning of the tunnel oxide layer in a floating gate memory integrated circuit.

Abstract: A novel dough-like mixture made using cellulose and hydrocolloid gums that can be used as a basis for forming a variety of low-calorie foods is disclosed. Methods for producing low-calorie and reduced-starch donuts, fillings, cookies, breads, and many other food products using this dough are also described. Erythritol-based reduced-sugar confectionery items and methods for their production and application, including use in reduced-calorie sweet-tasting bakery goods, are also disclosed. Many of the disclosed foods are low enough in caloric value to be termed “recreational solid foods,” with experiments showing that even ad libitum eating of them results in weight loss.

Abstract: A process of debugging application code includes stopping execution of the application, stepping backward through the code by line or instruction, stopping at a bug point in the code, modifying the state of the application at the bug point, and resuming execution of the application. A memory medium stores instructions executable by a processor to perform the process, or stores instructions executable by a processor to provide an interface that allows a user to perform the process. A system includes a processor that executes instructions to perform the process, or includes a processor that executes instructions to provide an interface that allows a user to perform the process.

Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.

Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.

Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.

Abstract: A system by which a software product may be tested on multiple client computers on various platforms. Product developers submit requests for tests on their products, in the form of test packets, to a test component, via an API. For each platform and language (i.e., group) on which a product developer wants a product tested, the product developer provides a test packet that defines tests that the product developer wants conducted on the product in that group. The test component searches, via an autolab component, for an available client machine for performing the tests in the test packet. The autolab component finds an available client computer, and the client machine is assigned the test packet. The client machine performs the tasks in the test packet, and forwards the results back to the test component.

Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.

Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.

Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.

Abstract: An interactive exercise system including exercise equipment having a resistance system, a speed sensor, a controller that varies the resistance setting of the exercise equipment, and a playback device for playing pre-recorded video and audio. The controller, operating in conjunction with speed information from the speed sensor and terrain information from media table files, dynamically varies the resistance setting of the exercise equipment in order to simulate varying degrees of difficulty while the playback device concurrently plays back the video and audio to create the simulation that the user is exercising in a natural setting such as a real-world exercise course.