Abstract: The present disclosure relates to implementing a secret mode in a social networking system. The secret mode provides a separate space for users to share and interact with particular friends. To implement the secret mode, each user may have a feed that is separate from the user's primary feed, the feed sometimes referred to as a secondary feed. Accordingly, a first user and a second user may each have a secondary feed. The first user may identify the second user as included in an audience of the first user. Based on the second using being included in the audience of the first user, content posted to the audience of the first user may be sent to the secondary feed of the second user such that the second user may view the content.

Abstract: A reciprocating syringe injector includes an inside arm and an outside arm pivotally mounted to the inside arm. A spring bias biases the inside arm away from the outside arm. A small syringe retainer is formed on the inside arm. A ratchet member extends from the inside arm toward the outside arm. The ratchet member has ratchet teeth protruding from the ratchet member. A ratchet engagement extension is pivotally mounted to the outside arm. The ratchet engagement extension has a ratchet engagement edge that engages the ratchet teeth formed on the ratchet member. The reciprocating syringe injector also optionally includes a large reservoir retainer mounted to the small syringe retainer. The large reservoir retainer could also be mounted anywhere on the inside arm.

Abstract: A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter.

Abstract: A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter.

Abstract: A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the circuit includes the Stall logic, the indicator and the counter.

Abstract: A clock recovery circuit samples an incoming data stream that includes sequences of signal transitions. A transition detector categorizes the received signal transitions into various types, such as those associated with 2PAM and 4PAM signaling schemes. Select logic control circuitry analyzes the signal-transition types to determine which of the transition types is best suited for clock recovery. This determination relies upon a number of factors, including for example whether the received signal is a 4PAM signal or a 2PAM signal, the existence of a pattern within the received data, or the relative abundance or scarcity of certain types of transitions.

Abstract: A computing system, method and computer readable media for group interactive multicast using UPnP AV architecture on a network are disclosed. The system comprises a plurality of devices and control points coupled to the network. The devices include a plurality of renders and a server, in which those renders form a group. The server comprises a data recording medium for saving a group list of the group. The control points comprise a server control point and a plurality of render control points. The control points are utilized to control the server and the renders and to register events. As one of the render control points correspondingly sends a command to one of the renders of the group, the render, which receives the command, will feedback a UPnP event to the server. The server will transfer the command to those renders, which do not receive the command before, so as to make those renders of the group to execute the command simultaneously.

Abstract: A method and system for enabling the sponsorship of document processing services. A document processing service request is submitted by an associated user. At least one sponsor, associated with the document processing service request is then identified and communicated to the user. Terms and conditions regarding the sponsorship of the request are then presented to the user for acceptance. The terms and conditions include restrictions on the number of pages, size and color, as well as the placement of an advertisement on the output. The advertisement is in the form of a banner, watermark or reverse-side image. Once accepted, the advertisement is inserted into the request and the selected operation is performed. The fees associated with the request are then calculated and charged to the sponsor. When only partial payment is authorized by the sponsor, the user is charged for the remaining fees.

Abstract: A clock recovery circuit samples an incoming data stream that includes sequences of signal transitions. A transition detector categorizes the received signal transitions into various types, such as those associated with 2PAM and 4PAM signaling schemes. Select logic control circuitry analyzes the signal-transition types to determine which of the transition types is best suited for clock recovery. This determination relies upon a number of factors, including for example whether the received signal is a 4PAM signal or a 2PAM signal, the existence of a pattern within the received data, or the relative abundance or scarcity of certain types of transitions.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter.

Abstract: A system and method that uses a pluggable preprocessor for monitoring a running job data stream that looks for header information to determine the appropriate queue for the job data stream. The data stream is then routed to the appropriate queue. The header information typically comprises a job name, an owner, and routing information. Thus, a print job will appear in the appropriate queue immediately while it is still being spooled. A job scheduler can trigger processing of the job when the processor is available and the job is ready for processing. This facilitates the handling of many jobs simultaneously segregated into their respective priority queues as soon as the clients send the jobs. Processing may then be serialized based on the processor load and job scheduling logic.

Abstract: An interface circuit providing a high speed bus. According to one embodiment, the interface circuitry includes a plurality of I/O pins coupled to a plurality of bus drivers, wherein each bus driver is configured to adjust the rise time, fall time, and drive strength of outputs signal on the I/O pins based on process-voltage-temperature ("PVT") conditions. The circuitry used to adjust the I/O outputs includes a slew rate control circuit, a current control circuit, and a delay lock loop ("DLL").