Abstract: In one embodiment, a method of determining changes between a first vector dataset and a second vector dataset includes receiving the first vector dataset and the second vector dataset, where each of the first vector dataset and the second vector dataset includes a plurality of features, each feature being defined by at least one vertex. The method also includes for each feature in the first vector dataset and the second vector dataset, generating a signature key based on geometric attributes of each feature, storing the signature key for each feature of the first vector dataset in a first data structure, storing the signature key for each feature of the second vector dataset in a second data structure, and comparing the first data structure to the second data structure to determine differences between the first vector dataset and the second vector dataset.

Abstract: A computer-implemented method is disclosed. The method includes: authenticating a user for login to a service for a first authenticated user session; in response to authenticating the user, sending, to a client device associated with the user, a first data string associated with a first validity period; receiving, from the client device after expiry of the first authenticated user session, a data access request to access protected data, the data access request including the first data string; validating the first data string based on checking the first validity period; and in response to determining that the first data string is valid, transmitting, to the client device, a data access response including at least a subset of the requested protected data.

Abstract: A semiconductor device includes a memory bank and first and second clock generators. The first clock generator includes a first transistor configured to receive an external clock signal. The first clock generator is configured to generate a global clock signal that is based on the external clock signal and that controls writing to and reading from the memory bank. The second clock generator includes a first transistor configured to receive the external clock signal. The second clock generator is configured to generate a pipeline clock signal that is based on the external clock signal and that controls a pipeline operation of reading from the memory bank. Methods of operating the first and second clock generators are also disclosed.

Abstract: A variety of methods, systems, and compositions are disclosed, including, in one embodiment, an additive manufacturing composition comprising an Fe—Cr—Ni alloy and a niobium-absorption element, wherein the Fe—Cr—Ni alloy has a niobium content of about 0.5% to about 5% by weight, wherein the niobium-absorption element forms a precipitate with niobium.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

Abstract: Methods and systems are presented for sharing detected changes in roads using blockchains in a network. The network includes vehicles operable to detect a change in a road, a plurality of local blockchains, and a global blockchain. The vehicles are divided into groups of local vehicles. The plurality of local blockchains includes local blocks of changes, wherein after a first vehicle publishes a change of the road among a group of local vehicles, a block of the change is integrated into a local blockchain when at least a local threshold number of the local vehicles endorse the change. The global blockchain includes blocks of changes, wherein a block of the change is integrated into the global blockchain when at least a global threshold number of the vehicles endorse the change. A token is awarded to the first vehicle.

Abstract: A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.

Abstract: A memory device includes one or more memory cells, and a pipeline coupled to the one or more memory cells. The memory device includes a first pulse generator coupled to the one or more memory cells. The first pulse generator is configured to generate, based on a first delayed clock signal, a memory clock signal to control the one or more memory cells. The first delayed clock signal is delayed with respect to a clock signal. The memory device includes a second pulse generator to generate, based on a second delayed clock signal and the memory clock signal, a pipeline clock signal to provide data from the one or more memory cells through the pipeline. The second delayed clock signal is delayed with respect to the clock signal.

Abstract: Systems, apparatuses, and methods may provide for technology for a releasable spacer associating a first printed circuit board with a second printed circuit board. The releasable spacer includes a first portion and a second portion. The first portion of the releasable spacer is attached to the first printed circuit board. The second portion of the releasable spacer is attached to the second printed circuit board. The releasable spacer is oriented and arranged to selectively couple and decouple the first printed circuit board from the second printed circuit board. The releasable spacer is oriented and arranged to permit airflow between the first printed circuit board and the second printed circuit board when selectively coupled.

Abstract: A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.

Abstract: A memory device includes one or more memory cells, and a pipeline coupled to the one or more memory cells. The memory device includes a first pulse generator coupled to the one or more memory cells. The first pulse generator is configured to generate, based on a first delayed clock signal, a memory clock signal to control the one or more memory cells. The first delayed clock signal is delayed with respect to a clock signal. The memory device includes a second pulse generator to generate, based on a second delayed clock signal and the memory clock signal, a pipeline clock signal to provide data from the one or more memory cells through the pipeline. The second delayed clock signal is delayed with respect to the clock signal.

Abstract: Circuits and methods are provided for a clock generation circuit that includes a first transistor, wherein a gate of the first transistor is connected to a clock signal, a second transistor, connected in parallel to the first transistor, and a driving circuit, coupled to the second transistor, and comprising an input and an output, wherein the input of the driving circuit is connected to the clock signal, the output of the driving circuit is connected to a gate of the second transistor, and the driving circuit is configured to reduce a slew of the clock signal.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

Abstract: According to an aspect of an embodiment operations may include receiving, by a server, message shares. The operations may also include generating, by the server, an aggregate hash share of the message shares. In addition, the operations may include receiving, by the server, a verification vector iteration from another server and generating another verification vector iteration based on: the received verification vector iteration, a permutation that corresponds to the server, and a masking vector that corresponds to the server. The operations may also include obtaining a verification hash that is based on the verification vector and participating in a multiparty computation to determine an aggregate hash. The operations may also include determining, as part of the multiparty computation, whether one or more of the servers is operating in an adverse manner based on whether the verification hash is equal to the aggregate hash.

Abstract: According to an aspect of an embodiment operations may include receiving, by a server, message shares. The operations may also include generating, by the server, an aggregate hash share of the message shares. In addition, the operations may include receiving, by the server, a verification vector iteration from another server and generating another verification vector iteration based on: the received verification vector iteration, a permutation that corresponds to the server, and a masking vector that corresponds to the server. The operations may also include obtaining a verification hash that is based on the verification vector and participating in a multiparty computation to determine an aggregate hash. The operations may also include determining, as part of the multiparty computation, whether one or more of the servers is operating in an adverse manner based on whether the verification hash is equal to the aggregate hash.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

Abstract: A computer-implemented method is disclosed. The method includes: authenticating a user for login to a service for a first authenticated user session; in response to authenticating the user, sending, to a client device associated with the user, a first data string associated with a first validity period; receiving, from the client device after expiry of the first authenticated user session, a data access request to access protected data, the data access request including the first data string; validating the first data string based on checking the first validity period; and in response to determining that the first data string is valid, transmitting, to the client device, a data access response including at least a subset of the requested protected data.

Abstract: A computer-implemented method is disclosed. The method includes: authenticating a user for login to a service for a first authenticated user session; in response to authenticating the user, generating a first data string associated with a first validity period; sending, to a client device associated with the user, the first data string; receiving, from the client device, a data access request to access a first data set at a remote data source, the data access request including the first data string; determining that the first authenticated user session has been terminated at a time of receiving the data access request; validating the first data string based on checking the first validity period; and in response to determining that the first authenticated user session has been terminated and that the first data string is valid, transmitting, to the client device, a data access response including at least a subset of the first data set.

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes one or more memory cells, and a pipeline coupled to the one or more memory cells. In one aspect, the memory device includes a first pulse generator coupled to the one or more memory cells. In some embodiments, the first pulse generator is configured to generate, based on a first delayed clock signal, a memory clock signal to control the one or more memory cells. In one aspect, the first delayed clock signal is delayed with respect to a clock signal. In one aspect, the memory device includes a second pulse generator to generate, based on a second delayed clock signal and the memory clock signal, a pipeline clock signal to provide data from the one or more memory cells through the pipeline. In one aspect, the second delayed clock signal is delayed with respect to the clock signal.

Abstract: Human monoclonal antibodies directed against B7-H1 and uses of these antibodies in diagnostics and for the treatment of diseases associated with the activity and/or expression of B7-H1 are disclosed. Additionally, hybridomas or other cell lines expressing such antibodies are disclosed.