Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

Abstract: According to an aspect of an embodiment operations may include receiving, by a server, message shares. The operations may also include generating, by the server, an aggregate hash share of the message shares. In addition, the operations may include receiving, by the server, a verification vector iteration from another server and generating another verification vector iteration based on: the received verification vector iteration, a permutation that corresponds to the server, and a masking vector that corresponds to the server. The operations may also include obtaining a verification hash that is based on the verification vector and participating in a multiparty computation to determine an aggregate hash. The operations may also include determining, as part of the multiparty computation, whether one or more of the servers is operating in an adverse manner based on whether the verification hash is equal to the aggregate hash.

Abstract: According to an aspect of an embodiment operations may include receiving, by a server, message shares. The operations may also include generating, by the server, an aggregate hash share of the message shares. In addition, the operations may include receiving, by the server, a verification vector iteration from another server and generating another verification vector iteration based on: the received verification vector iteration, a permutation that corresponds to the server, and a masking vector that corresponds to the server. The operations may also include obtaining a verification hash that is based on the verification vector and participating in a multiparty computation to determine an aggregate hash. The operations may also include determining, as part of the multiparty computation, whether one or more of the servers is operating in an adverse manner based on whether the verification hash is equal to the aggregate hash.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

Abstract: A computer-implemented method is disclosed. The method includes: authenticating a user for login to a service for a first authenticated user session; in response to authenticating the user, sending, to a client device associated with the user, a first data string associated with a first validity period; receiving, from the client device after expiry of the first authenticated user session, a data access request to access protected data, the data access request including the first data string; validating the first data string based on checking the first validity period; and in response to determining that the first data string is valid, transmitting, to the client device, a data access response including at least a subset of the requested protected data.

Abstract: A computer-implemented method is disclosed. The method includes: authenticating a user for login to a service for a first authenticated user session; in response to authenticating the user, generating a first data string associated with a first validity period; sending, to a client device associated with the user, the first data string; receiving, from the client device, a data access request to access a first data set at a remote data source, the data access request including the first data string; determining that the first authenticated user session has been terminated at a time of receiving the data access request; validating the first data string based on checking the first validity period; and in response to determining that the first authenticated user session has been terminated and that the first data string is valid, transmitting, to the client device, a data access response including at least a subset of the first data set.

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes one or more memory cells, and a pipeline coupled to the one or more memory cells. In one aspect, the memory device includes a first pulse generator coupled to the one or more memory cells. In some embodiments, the first pulse generator is configured to generate, based on a first delayed clock signal, a memory clock signal to control the one or more memory cells. In one aspect, the first delayed clock signal is delayed with respect to a clock signal. In one aspect, the memory device includes a second pulse generator to generate, based on a second delayed clock signal and the memory clock signal, a pipeline clock signal to provide data from the one or more memory cells through the pipeline. In one aspect, the second delayed clock signal is delayed with respect to the clock signal.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

Abstract: Human monoclonal antibodies directed against B7-H1 and uses of these antibodies in diagnostics and for the treatment of diseases associated with the activity and/or expression of B7-H1 are disclosed. Additionally, hybridomas or other cell lines expressing such antibodies are disclosed.

Abstract: Disclosed herein are system, method, and computer program product embodiments for mapping API dependencies for a journey test. An embodiment operates by receiving, at a graphical user interface (GUI), a test script representing the user journey within an application, wherein the test script specifies a sequence of application programming interfaces (APIs) that have been called as a user journeys through the application. The embodiment generates an API dependency map within the GUI comprising a sequential map of visual objects, illustrating (1) each of the APIs specified in the test script and (2) any dependent API called by each of the APIs. The embodiment executes the test script representing the user journey. The embodiment generates a status corresponding to each of the APIs called when executing the test script. The embodiment causes display of the generated status of an API or dependent API within the GUI selected by the user.

Abstract: A semiconductor device includes a memory bank and first and second clock generators. The first clock generator includes a first transistor configured to receive an external clock signal. The first clock generator is configured to generate a global clock signal that is based on the external clock signal and that controls writing to and reading from the memory bank. The second clock generator includes a first transistor configured to receive the external clock signal. The second clock generator is configured to generate a pipeline clock signal that is based on the external clock signal and that controls a pipeline operation of reading from the memory bank. Methods of operating the first and second clock generators are also disclosed.

Abstract: Devices and methods for providing alert notifications. The device includes an input module, a display, and memory having instructions. The device receives, via the input module, a first signal representing a command to set an alert condition associated with an identifier and, in response, generates the alert condition. The device transmits a second signal representing the alert condition to a monitoring system for setting up a targeted notification. The device receives a third signal representing an asserted alert indicating that the alert condition is satisfied and displays on the display, based on the third signal representing the asserted alert, an alert notification including the identifier and a first selectable option associated with a first application interface. In response to receiving, via the input module, a fourth signal representing selection of the first selectable option, the device displays the first application interface and auto-populates a first field based on the identifier.

Abstract: Human monoclonal antibodies directed against B7-H1 and uses of these antibodies in diagnostics and for the treatment of diseases associated with the activity and/or expression of B7-H1 are disclosed. Additionally, hybridomas or other cell lines expressing such antibodies are disclosed.

Abstract: A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.

Abstract: The present invention relates to novel antibodies, particularly antibodies directed against deletion mutants of epidermal growth factor receptor and particularly to the type III deletion mutant, EGFRvIII. The invention also relates to human monoclonal antibodies directed against deletion mutants of epidermal growth factor receptor and particularly to EGFRvIII. Diagnostic and therapeutic formulations of such antibodies, and immunoconjugates thereof, are also provided.

Abstract: A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.

Abstract: A computer-implemented method is disclosed. The method includes: authenticating a user for login to a service for a first authenticated user session; in response to authenticating the user, generating a first data string associated with a first validity period; sending, to a client device associated with the user, the first data string; receiving, from the client device, a data access request to access a first data set at a remote data source, the data access request including the first data string; determining that the first authenticated user session has been terminated at a time of receiving the data access request; validating the first data string based on checking the first validity period; and in response to determining that the first authenticated user session has been terminated and that the first data string is valid, transmitting, to the client device, a data access response including at least a subset of the first data set.

Abstract: A method for real-time processing of data retrieval requests is disclosed. The method includes: receiving, from a client device, a first login request to log in to a service; authenticating the user for login to the service; in response to authenticating the user, generating a first data string representing at least a unique device identifier for the client device and a validity period; storing the device identifier; sending, to the client device, the first data string; receiving, from the client device, a data retrieval request to retrieve a data set from a remote server, the data retrieval request including the first data string; determining whether the first data string is valid based on checking the validity period; in response to determining that the first data string is valid: obtaining the data set from the remote server; and sending, to the client device, first data based on the obtained data set.

Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.

Abstract: Examples described herein includes initialization of a computing node cluster. An example method providing a query request from an initialization application/service of a computing node for a default configuration management server identifier via a network, and receiving, from a network management server, an internet protocol address associated with the default configuration management server identifier. The example method further includes providing a configuration request from the computing node to the internet protocol address requesting configuration information, and receiving the configuration information at the computing node from a configuration management server associated with the internet protocol address.