Patents by Inventor Jaspreet Singh

Jaspreet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10417020
    Abstract: According to some aspects disclosed herein, a system for remote assistance and control of user devices subject to one or more remote assistance policies may be provided. In some embodiments, an administrator may request remote control of a managed user device. A managed application launcher may be provided by the user device and may be modified by the user device to remove managed applications or otherwise prevent access to applications that have a policy indicating that remote assistance is not allowed. The administrator may open a managed application included in the launcher and remotely control that application. In other embodiments, a user of the managed user device may initiate a request for remote assistance from within a managed application and/or the managed application launcher. The administrator's control of the user device and access to other applications on the user device may be limited based on the remote assistance policies.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 17, 2019
    Assignee: Citrix Systems, Inc.
    Inventors: Nitin Desai, Jaspreet Singh
  • Patent number: 10403591
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 3, 2019
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Publication number: 20190259695
    Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.
    Type: Application
    Filed: February 22, 2018
    Publication date: August 22, 2019
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Vadim Heyfitch
  • Patent number: 10362612
    Abstract: Methods and systems for enabling multiple mobile devices to access an access gateway when at least one of the multiple mobile devices is unable to establish a virtual private network connection with the access gateway are described herein. For example, in some embodiments, a mobile device may configure itself as a member of a mesh network. A virtual private network connection may be established between the mobile device and the access gateway. The mesh network may include one or more other member devices that are unable to establish a virtual private network with the access gateway. After completing its configuration, the mobile device may receive, over a peer-to-peer connection of the mesh network, data that is intended for the access gateway and that is from one of the other member devices. The mobile device may transmit the data to the access gateway via the virtual private network connection.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 23, 2019
    Assignee: Citrix Systems, Inc.
    Inventors: Chakravarthi Valicherla, Grant Kennell, Jaspreet Singh
  • Patent number: 10349313
    Abstract: A method of coordinating a plurality of radio access networks (RANs) includes aggregating, with a gateway, communications interfaces between a plurality of RANs and a packet core network through the gateway. A plurality of radio nodes (RNs) in each of the RANs is communicatively coupled to the gateway and to user equipment (UE) devices associated with the RNs in each of the RANs. The gateway also controls and coordinates mobility of the UE devices within and among the RANs.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 9, 2019
    Assignee: Corning Optical Communications LLC
    Inventors: Tsung-Yi Chen, Jaspreet Singh, Peter J. Worters
  • Patent number: 10319606
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, Ivor G. Barber, Suresh Ramalingam
  • Publication number: 20190131265
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 2, 2019
    Applicant: Xilinx, Inc.
    Inventor: Jaspreet Singh Gandhi
  • Patent number: 10272233
    Abstract: The present disclosure relates generally to microneedle devices and methods for fabricating microneedles from a biocompatible polymer using photolithography. More particularly, aspects of the present disclosure are directed to the fabrication of microneedle devices using a biocompatible polymer (biopolymer) by way of biocompatible, essentially biocompatible, or substantially biocompatible fabrication techniques.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 30, 2019
    Assignee: National University of Singapore
    Inventors: Lifeng Kang, Sui Yung Chan, Jaspreet Singh Kochhar, Wei Jiang Goh
  • Patent number: 10236229
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (IC) dies, a packaging substrate, and a lid. The packaging substrate has a die receiving area that is defined by the laterally outermost extents of the IC dies mounted to the packaging substrate. The lid a surface that includes a first region and a second region. The first region is disposed over the first IC die while the second region of the lid extends below the second surface the first IC die and is spaced above the packaging substrate. At least a portion of the second region of the lid is overlapped with the die receiving area.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 19, 2019
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Publication number: 20190073384
    Abstract: A method for automatically managing a plurality of slides associated with a slide-deck is provided. The method may include adding the plurality of slides to a computing system. The method may also include analyzing at least one slide within the plurality of slides. The method may further include generating a list including at least one key word or at least one tag based on the analyzing. The method may include matching the at least one key word or the at least one tag against at least one key word or at least one tag saved on a presentation server. The method may also include fetching at least one slide or at least one slide-deck from the presentation server based on the matching. The method may further include displaying the at least one fetched slide or the at least one fetched slide-deck on a user interface.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 7, 2019
    Inventors: Andreas Nauerz, Isabell Sippli, Jaspreet Singh, Martin Welsch
  • Publication number: 20190057099
    Abstract: Structured data archival with reduced downtime is disclosed. One example is a system including a deployer that manages an active table (AT), and a non-active table (NAT), and creates an intermediate table (IT) to record, during data archival, changes to the data to be archived. The deployer creates triggers on the AT and the NAT to facilitate the record, by the IT, of the changes to the data to be archived. An archiver initiates the data archival by archiving the copy of the data to be archived from the NAT, merges the recorded data from the IT to the NAT upon receiving an indication that the client access to the AT is not enabled, and switches the client access from the AT to the NAT by changing a table synonym, where the client access to the NAT is enabled upon completion of the data archival.
    Type: Application
    Filed: April 8, 2016
    Publication date: February 21, 2019
    Inventors: Danny Oberoi, Jaspreet Singh, Ibha Gandhi
  • Publication number: 20190053248
    Abstract: A method is shown for allocating a plurality of channels to a plurality of radio nodes (RNs) in a radio access network (RAN). In accordance with the method, an initial RN is selected from among the plurality of RNs. A first of the plurality of channels is assigned to the initial RN. The first channel is selected such that external interference experienced by the initial RN from sources other than the RAN on the first channel is minimized. A second RN is selected from among the plurality of RNs. A second of the plurality of channels is assigned to the second RN. The second channel is selected such that a metric reflective of an information carrying capacity of the RNs that have already been assigned one of the plurality of channels is maximized. The assigned channels are allocated to the respective RNs to which they have been assigned.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Inventors: Tsung-Yi Chen, Hithesh Nama, Jaspreet Singh
  • Publication number: 20180358280
    Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 13, 2018
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10146800
    Abstract: A method for automatically managing a plurality of slides associated with a slide-deck is provided. The method may include adding the plurality of slides to a computing system. The method may also include analyzing at least one slide within the plurality of slides. The method may further include generating a list including at least one key word or at least one tag based on the analyzing. The method may include matching the at least one key word or the at least one tag against at least one key word or at least one tag saved on a presentation server. The method may also include fetching at least one slide or at least one slide-deck from the presentation server based on the matching. The method may further include displaying the at least one fetched slide or the at least one fetched slide-deck on a user interface.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andreas Nauerz, Jaspreet Singh, Isabell Sippli, Martin Welsch
  • Patent number: 10146798
    Abstract: A method for automatically managing a plurality of slides associated with a slide-deck is provided. The method may include adding the plurality of slides to a computing system. The method may also include analyzing at least one slide within the plurality of slides. The method may further include generating a list including at least one key word or at least one tag based on the analyzing. The method may include matching the at least one key word or the at least one tag against at least one key word or at least one tag saved on a presentation server. The method may also include fetching at least one slide or at least one slide-deck from the presentation server based on the matching. The method may further include displaying the at least one fetched slide or the at least one fetched slide-deck on a user interface.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andreas Nauerz, Jaspreet Singh, Isabell Sippli, Martin Welsch
  • Publication number: 20180324818
    Abstract: A method for assessing an impact of a design choice on a system level performance metric of a radio access network (RAN) deployed in an environment includes receiving messages from a plurality of UEs over time by a plurality of RNs in the RAN. A design choice is selected for a set of operating parameters of the RAN. One or more of measurement values in each of the received messages and the selected design choice are processed to compute a set of derivatives. A system level performance metric is determined as a function of the computed set of derivatives.
    Type: Application
    Filed: July 16, 2018
    Publication date: November 8, 2018
    Inventors: Tsung-Yi Chen, Hithesh Nama, Jaspreet Singh
  • Patent number: 10111235
    Abstract: A method is shown for allocating a plurality of channels to a plurality of radio nodes (RNs) in a radio access network (RAN). In accordance with the method, an initial RN is selected from among the plurality of RNs. A first of the plurality of channels is assigned to the initial RN. The first channel is selected such that external interference experienced by the initial RN from sources other than the RAN on the first channel is minimized. A second RN is selected from among the plurality of RNs. A second of the plurality of channels is assigned to the second RN. The second channel is selected such that a metric reflective of an information carrying capacity of the RNs that have already been assigned one of the plurality of channels is maximized. The assigned channels are allocated to the respective RNs to which they have been assigned.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: October 23, 2018
    Assignee: SpiderCloud Wireless, Inc.
    Inventors: Jaspreet Singh, Tsung-Yi Chen, Hithesh Nama
  • Patent number: 10096502
    Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: October 9, 2018
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Mohsen H. Mardi, Tien-Yu Lee, Ivor G. Barber, Cheang-Whang Chang, Jaspreet Singh Gandhi
  • Publication number: 20180284187
    Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Applicant: Xilinx, Inc.
    Inventors: Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, David M. Mahoney, Mohsen H. Mardi
  • Publication number: 20180286826
    Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam, Henley Liu