Patents by Inventor Jaspreet Singh

Jaspreet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200188293
    Abstract: Provided herein is a personal care composition that can exhibit an increased vapor release while maintaining physical stability and texture. The personal care composition can contain from about 35% to about 90% petrolatum, from about 20% to about 50% of an olfactory composition, and a gelling agent mixture. The gelling agent mixture can contain dibutyl lauroyl glutamide, dibutyl ethylhexanoyl glutamide, and a solvent selected from the group consisting of pentylene glycol, propylene glycol, hexylene glycol, 3-methyl-1,3-butanediol, 3-methyl-1,2-butanediol, 1,5-pentanediol, and combinations thereof. The personal care composition can exhibit a vapor release of from about 35 mg to about 300 mg at 8 hours and can have an Instability Index of less than about 0.8.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 18, 2020
    Inventors: Stephen Bingham, Barbara Jackova, Joshua Hampton, Jason William Newlon, Jaspreet Singh Kochhar, Jayant Khanolkar, Aline Fornear
  • Publication number: 20200185686
    Abstract: A battery pack for a vehicle electrical system configured with high-voltage bus bars. A positive bus bar and a negative bus bar may provide power generated by the battery pack to a drive module of the vehicle, to power one or more components of the vehicle. The drive module may additionally couple to high-voltage positive and negative bus bars. The high-voltage bus bars may be configured to provide additional power to the drive module from another battery pack, such as via a battery balance box. Additionally, the high-voltage bus bars may be configured to carry excess power from the drive module to another drive module associated with the vehicle via the battery balance box. The high-voltage bus bars may be configured to de-energize in the event of a thermal runaway or other failure of a battery module of the associated battery pack.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 11, 2020
    Inventors: Robert Alan Ng, Moritz Boecker, Kyle Matthew Foley, Jason Jaspreet Singh Haer, David Sands
  • Publication number: 20200185671
    Abstract: A battery pack for a vehicle electrical system includes a casing for receiving one or more battery modules. The battery modules are insertable into a casing of the battery pack by sliding couplers along pairs of rails and are securable to the ends of the rails. After insertion, the rails thermally insulate one battery module from other battery modules in the battery pack. Additionally, the battery modules may include a top cover with an insulating material to further thermally insulate one battery module from another battery module. The battery pack may additionally be configured with vents for venting the hot gases, such as those generated by a battery module in a thermal runaway event. Additionally, the battery modules may include a second insulating material disposed between cells and configured to thermally insulate the cells from one another.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 11, 2020
    Inventors: Robert Alan Ng, Moritz Boecker, Kyle Matthew Foley, Jason Jaspreet Singh Haer, David Sands
  • Publication number: 20200161229
    Abstract: An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Applicant: Xilinx, Inc.
    Inventor: Jaspreet Singh Gandhi
  • Patent number: 10642888
    Abstract: A method for automatically managing a plurality of slides associated with a slide-deck is provided. The method may include adding the plurality of slides to a computing system. The method may also include analyzing at least one slide within the plurality of slides. The method may further include generating a list including at least one key word or at least one tag based on the analyzing. The method may include matching the at least one key word or the at least one tag against at least one key word or at least one tag saved on a presentation server. The method may also include fetching at least one slide or at least one slide-deck from the presentation server based on the matching. The method may further include displaying the at least one fetched slide or the at least one fetched slide-deck on a user interface.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andreas Nauerz, Isabell Sippli, Jaspreet Singh, Martin Welsch
  • Patent number: 10638326
    Abstract: A method for assigning a percentage of a CSAT time cycle to each radio node (RN) in a plurality of RNs that belong to a small cell radio access network (RAN) having a central controller includes: (i) for each time cycle period during which the RNs share a channel with one or more nodes that employ a different radio access technology (RAT), assigning a default occupancy percentage of the time cycles to each of the RNs; (ii) determining if the default occupancy percentage is able to be increased without violating one or more co-existence principles pre-established for the RAT employed by the RNs in the RAN and the different RAT; (iii) increasing the occupancy percentage of the first RN if it is determined that the default occupancy percentage is able to be increased without violating the co-existence principles; and (iv) sequentially repeating (ii)-(iii) for each remaining RN in the RAN.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 28, 2020
    Assignee: Corning Optical Communications LLC
    Inventors: Jaspreet Singh, Tsung-Yi Chen, Hithesh Nama
  • Publication number: 20200111555
    Abstract: The present disclosure concerns the synchronization of hierarchical data between a sender and a recipient using hash codes. Hierarchical hash codes are used for synchronization of IT systems. The hierarchy of forwarded objects is condensed in the hierarchical hash codes which are exchanged between the IT systems. The complete hierarchy of the underlying and associated child objects is condensed in each hash code of a parent object: identifiers of the child objects and the relationships of the child objects below the parent object with one another and with the parent object. This applies to each aggregation level, so that the hash code of the at least one top element represents the complete hierarchy.
    Type: Application
    Filed: July 21, 2017
    Publication date: April 9, 2020
    Applicant: BAYER BUSINESS SERVICES GMBH
    Inventors: Hermann HERTER, Jaspreet Singh MAROK, Andrej CEH
  • Publication number: 20200105642
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
  • Patent number: 10606728
    Abstract: Methods and system are disclosed that determine anomalies in the source code in a procedural program paradigm. In one aspect, an input to analyze source code may be received via an integrated development environment. Upon receiving the input, a source code analyzer model may be instantiated at a framework. Based on decision logic associated with the procedural programming paradigm, the source code may be analyzed by the instantiated source code analyzer model at the framework. In response to the analysis, anomalies associated with the source code may be determined at the framework. Upon determining the anomalies, a user interface model may be instantiated at the framework. The instantiated user interface model may provide a user interface that may display a list of solutions in response to the determined anomalies in the source code. An end user may select the solution that may be inserted into the source code.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 31, 2020
    Assignee: SAP SE
    Inventors: Rajinder Pal Singh, Jaspreet Singh, Vishu Agarwal
  • Patent number: 10593638
    Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: March 17, 2020
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam, Henley Liu
  • Publication number: 20200035635
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam
  • Patent number: 10546319
    Abstract: A method for selecting advertisements to embed in an online application, including detecting an access to the online application by a customer, determining, based on an impression tracker associated with the customer, and using an ad type selection model, an advertisement to embed in the online application. The advertisement is displayed to the user and the impression tracker associated with the customer is incremented. The method further includes receiving, from the user, a selection of the advertisement, storing a type of the advertisement and the value of the impression tracker as ad selection data, determining that the ad type selection model needs to be updated, and updating the ad type selection model based on the ad selection data to obtain an updated ad type selection model.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: January 28, 2020
    Assignee: Intuit Inc.
    Inventors: Houtao Deng, John A. Bocharov, S. Satishkumar, Sean Arnold Pudney, Jaspreet Singh
  • Patent number: 10527670
    Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, David M. Mahoney, Mohsen H. Mardi
  • Patent number: 10529645
    Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10448410
    Abstract: A method is shown for allocating a plurality of channels to a plurality of radio nodes (RNs) in a radio access network (RAN). In accordance with the method, an initial RN is selected from among the plurality of RNs. A first of the plurality of channels is assigned to the initial RN. The first channel is selected such that external interference experienced by the initial RN from sources other than the RAN on the first channel is minimized. A second RN is selected from among the plurality of RNs. A second of the plurality of channels is assigned to the second RN. The second channel is selected such that a metric reflective of an information carrying capacity of the RNs that have already been assigned one of the plurality of channels is maximized. The assigned channels are allocated to the respective RNs to which they have been assigned.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: October 15, 2019
    Assignee: Corning Optical Communications LLC
    Inventors: Tsung-Yi Chen, Hithesh Nama, Jaspreet Singh
  • Publication number: 20190306762
    Abstract: A method of coordinating a plurality of radio access networks (RANs) includes aggregating, with a gateway, communications interfaces between a plurality of RANs and a packet core network through the gateway. A plurality of radio nodes (RNs) in each of the RANs is communicatively coupled to the gateway and to user equipment (UE) devices associated with the RNs in each of the RANs. The gateway also controls and coordinates mobility of the UE devices within and among the RANs.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Inventors: Tsung-Yi Chen, Jaspreet Singh, Peter J Worters
  • Publication number: 20190289656
    Abstract: Methods and systems for enabling multiple mobile devices to access an access gateway when at least one of the multiple mobile devices is unable to establish a virtual private network connection with the access gateway are described herein. For example, in some embodiments, a mobile device may configure itself as a member of a mesh network. A virtual private network connection may be established between the mobile device and the access gateway. The mesh network may include one or more other member devices that are unable to establish a virtual private network with the access gateway. After completing its configuration, the mobile device may receive, over a peer-to-peer connection of the mesh network, data that is intended for the access gateway and that is from one of the other member devices. The mobile device may transmit the data to the access gateway via the virtual private network connection.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Inventors: Chakravarthi Valicherla, Grant Kennell, Jaspreet Singh
  • Patent number: 10417020
    Abstract: According to some aspects disclosed herein, a system for remote assistance and control of user devices subject to one or more remote assistance policies may be provided. In some embodiments, an administrator may request remote control of a managed user device. A managed application launcher may be provided by the user device and may be modified by the user device to remove managed applications or otherwise prevent access to applications that have a policy indicating that remote assistance is not allowed. The administrator may open a managed application included in the launcher and remotely control that application. In other embodiments, a user of the managed user device may initiate a request for remote assistance from within a managed application and/or the managed application launcher. The administrator's control of the user device and access to other applications on the user device may be limited based on the remote assistance policies.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 17, 2019
    Assignee: Citrix Systems, Inc.
    Inventors: Nitin Desai, Jaspreet Singh
  • Patent number: 10403591
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 3, 2019
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Publication number: 20190259695
    Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.
    Type: Application
    Filed: February 22, 2018
    Publication date: August 22, 2019
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Vadim Heyfitch